Abstract
The design of heterogeneous Systems-on-Chips (SoC) in very deep submicron technologies has become a very complex task that has to bridge very high level system descriptions with low-level considerations due to technology defaults and variations, and increasing system and circuit complexity. This paper describes the major low-level issues, such as dynamic and static power consumption, temperature, technology variations, interconnect, Design for Manufacturing (DFM), reliability and yield, and their impact on high-level design, such as the design of multi-V dd , fault-tolerant, redundant or adaptive chip architectures. Some multi-processor based SoC (MPSoC) cases are also presented in three domains in which heterogeneity is large: wireless sensor networks, vision sensors and mobile TV. These examples also highlight the heterogeneous nature and the increasing complexity at circuit-level, with the extension from CMOS-only SoCs towards MEMS-and-CMOS SoCs.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Enz, C., et al.: WiseNET: an ultra-low power wireless sensor network solution. Computer 37, 62–70 (2004)
Rabaey, J.: Managing power dissipation in the generation-after-next wireless systems. In: FTFC’99, Paris, France, June 1999
Vittoz, E.: Weak inversion for ultimate low-power logic. In: Piguet, C. (ed.) Low-Power Electronics Design. CRC Press, Boca Raton (2004). Chap. 16
Hanson, S., Zhai, B., Blaauw, D., Sylvester, D., Bryant, A., Wang, X.: Energy optimality and variability in subthreshold design. In: Intl. Symp. on Low Power Electronics and Design, pp. 363–365 (2006)
Henzinger, T., Sifakis, J.: The discipline of embedded systems design. Computer 40, 32–40 (2007)
Arm, C., Masgonty, J.-M., Piguet, C.: Double-latch clocking scheme for low-power I.P. Cores. In: PATMOS, Goettingen, Germany, September 13–15, 2000
Donno, M., Ivaldi, A., Benini, L., Macii, E.: Clock-tree power optimization based on RTL clock-gating. In: Proc. DAC’03, 40th Design Automation Conference (DAC’03), p. 622 (2003)
Benini, L., et al.: A refinement methodology for clock gating optimization at layout level in digital circuits. J. Low Power Electron. 6(1), 44–55 (2010)
Arm, C., Masgonty, J.-M., Morgan, M., Piguet, C., Pfister, P.-D., Rampogna, F., Volet, P.: Low-power quad MAC 170 μW/MHz 1.0 V MACGIC DSP core. In: ESSCIRC, Montreux, Switzerland, Sept. 19–22, 2006
Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91(2), 305–327 (2003)
Schuster, C., Nagel, J.-L., Piguet, C., Farine, P.-A.: Leakage reduction at the architectural level and its application to 16 bit multiplier architectures. In: PATMOS ’04, Santorini Island, Greece, September 15–17, 2004
Schuster, C., Piguet, C., Nagel, J.-L., Farine, P.-A.: An architecture design methodology for minimal total power consumption at fixed V dd and V th . J. Low Power Electron. 1(1), 1–8 (2005)
Schuster, C., Nagel, J.-L., Piguet, C., Farine, P.-A.: Architectural and technology influence on the optimal total power consumption. In: DATE 2006, Munich, March 6–10, 2006
Zhai, B., Blaauw, D., Sylvester, D., Flautner, K.: Theoretical and practical limits of dynamic voltage scaling. In: DAC 2004, pp. 868–873 (2004)
Hanson, S., Zhai, B., Blaauw, D., Sylvester, D., Bryant, A., Wang, X.: Energy optimality and variability in subthreshold design. In: International Symposium on Low Power Electronics and Design, ISLPED 2006, pp. 363–365 (2006)
Kwong, J., et al.: A 65 nm Sub-Vt microcontroller with integrated SRAM and switched-capacitor DC-DC converter. In: ISSCC’08, pp. 318–319 (2008)
Piguet, C., Berweiler, G., Voirol, C., Dijkstra, E., Rijmenants, J., Zinszner, R., Stauffer, M., Joss, M.: ALADDIN: a CMOS gate-matrix layout system. In: Proc. of ISCAS 88, Espoo, Helsinki, Finland, p. 2427 (1988)
Haykel Ben Jamaa, M., Moselund, K.E., Atienza, D., Bouvet, D., Ionescu, A.M., Leblebici, Y., De Micheli, G.: Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. In: Proc. ICCAD’07, pp. 765–772
Peiris, V., et al.: A 1 V 433/868 MHz 25 kb/s-FSK 2 kb/s-OOK RF transceiver SoC in standard digital 0.18 μm CMOS. In: Int. Solid-State Circ. Conf. Dig. of Tech. Papers, Feb. 2005, pp. 258–259 (2005)
El-Hoiydi, A., Decotignie, J.-D., Enz, C., Le Roux, E.: WiseMAC, an ultra low power MAC protocol for the WiseNET wireless sensor network. In: SenSys’03, Los Angeles, CA, USA, November 5–7, 2003
Arm, C., Gyger, S., Masgonty, J.-M., Morgan, M., Nagel, J.-L., Piguet, C., Rampogna, F., Volet, P.: Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU core. In: ESSCIRC, Edinburgh, Scotland, UK, Sept. 15–19, 2008
Huang, Yu, et al.: Logic gates and computation from assembled nanowire building blocks. Science 294, 1313–1316 (2001)
Schmid, A., Leblebici, Y.: Array of nanometer-scale devices performing logic operations with fault-tolerant capability. In: Fourth IEEE Conference on Nanotechnology IEEE-NANO (2004)
Ecoffey, S., Pott, V., Bouvet, D., Mazza, M., Mahapatra, S., Schmid, A., Leblebici, Y., Declercq, M.J., Ionescu, A.M.: Nano-wires for room temperature operated hybrid CMOS-NANO integrated circuits. In: Solid-State Circuits Conference, ISSCC 2005, 6–10 Feb. 2005, pp. 260–597, vol. 1 (2005)
Frei, J., et al.: Body effect in tri- and pi-gate SOI MOSFETS. IEEE Electron Device Lett. 25(12), 813–815 (2004)
Singh, N., et al.: High-performance fully depleted silicon nanowire (diameter < 5 nm) gate-all-around CMOS devices. IEEE Electron Device Lett. 27(5), 383–386 (2006)
Kheradmand Boroujeni, B., et al.: Reverse Vgs (RVGS): a new method for controlling power and delay of logic gates in sub-VT regime. Invited talk at VLSI-SoC, Rhodes Island, Oct. 13–15, 2008
Acknowledgements
The authors wish to acknowledge the CSEM design teams that contributed to the SoC cases described above: Claude Arm, Flavio Rampogna, Silvio Todeschini, Ricardo Caseiro of the “SoC and Digital Group”, Pierre-François Ruedi, Edoardo Franzi, François Kaess, Eric Grenet, Pascal Heim, Pierre Alain Beuchat, of the “Vision Sensor Group”, D. Ruffieux, F. Pengg, M. Kucera, A. Vouilloz, J. Chabloz, M. Contaldo, F. Giroud, N. Raemy of the “RF and Analog IC Group” and E. Le Roux, P. Volet of the “Digital Radio Group”.
The authors also wish to acknowledge the EU project MAP2 partners (CRAFT-031984), i.e. OFFIS, ChipVision, Politecnico di Torino and BullDAST, for the design methodologies described in Sect. 3. The authors also acknowledge the industrial contributions from Hager and Semtech for the WiseNET SoC, and Abilis for the MACGIC-based SoC for mobile TV.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer Science+Business Media B.V.
About this chapter
Cite this chapter
Piguet, C. et al. (2012). Trends in Design Methods for Complex Heterogeneous Systems. In: Nicolescu, G., O'Connor, I., Piguet, C. (eds) Design Technology for Heterogeneous Embedded Systems. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1125-9_9
Download citation
DOI: https://doi.org/10.1007/978-94-007-1125-9_9
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-007-1124-2
Online ISBN: 978-94-007-1125-9
eBook Packages: EngineeringEngineering (R0)