Abstract
Many-core platforms, providing large numbers of parallel execution resources, emerge as a response to the increasing computation needs of embedded applications. A major challenge raised by this trend is the efficient mapping of applications on parallel resources. This is a non-trivial problem because of the number of parameters to be considered for characterizing both the applications and the underlying platform architectures. Recently, several authors have proposed to use Multi-Objective Evolutionary Algorithm (MOEA) to solve this problem within the context of mapping applications on Network-on-Chips (NoC). However, these proposals have several limitations: (1) only few meta-heuristics are explored (mainly NSGAII and SPEA2), (2) only few objective functions are provided, and (3) they only deal with a small number of the application and architecture constraints. In this chapter, we propose a new framework which avoids all of the problems cited above. Our framework is implemented on top of the jMetal framework which offers an extensible environment. Our framework allows designers to (1) explore several new meta-heuristics, (2) easily add a new objective function (or to use an existing one) and (3) take into account any number of architecture and application constraints. The chapter also presents experiments illustrating how our framework is applied to the problem of mapping streaming applications on a NoC based many-core platform. Our results show that several new meta-heuristics outperform the classical multi-objective meta-heuristics such as NSGAII and SPEA2. Moreover, a parallel multi-objective evolutionary algorithm is implemented in our framework in order to increase the explored space of solutions by simultaneously running several meta-heuristics.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Garey, M.R., Johnson, D.S.: Computers and Intractability: A Guide to the Theory of NP-Completeness. Freeman, New York (1979)
Ascia, G., Catania, V., Palesi, M.: Mapping cores on network-on-chip. Int. J. Comput. Intell. Res. 1(1–2), 109–126 (2005)
Erbas, C., Cerav-erbas, S., Pimentel, A.D.: Multi-objective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design. IEEE Trans. Evol. Comput. 10(3), 358–374 (2006)
Jena, R.K., Sharma, G.K.: A multi-objective evolutionary algorithm-based optimisation model for network on chip synthesis. Int. J. Innov. Comput. Appl. 1(2), 121–127 (2007)
Lei, T., Kumar, S.: A two-step genetic algorithm for mapping task graphs to a network on chip architecture. In: DSD (2003)
Deb, K., Pratap, A., Agarwal, S., Meyarivan, T.: A fast and elitist multi-objective genetic algorithm: NSGA-II. IEEE Trans. Evol. Comput. 6(2), 182–197 (2002)
Zitzler, E., Laumanns, M., Thiele, L.: SPEA2: improving the performance of the strength Pareto evolutionary algorithm. Technical Report 103, Computer Engineering and Communication Networks Lab (TLK), Swiss Federal Institute of Technology (2001)
Coello Coello, C.A., Veldhuizen, D.A.V., Lamont, G.B.: Evolutionary Algorithms for Solving Multi-objective Problems. Kluwer Academic, Dordrecht (2002)
Das, I.: Nonlinear multi-criteria optimization and robust optimality. Ph.D. Thesis, Dept. of Computational and Applied Mathematics, Rice University, Houston, TX (1997)
Nebro, A.J., Durillo, J.J., Luna, F., Dorronsoro, B., Alba, E.: MOCell: A cellular genetic algorithm for multi-objective optimization. Int. J. Intell. Syst. 24(7), 726–746 (2009)
Nebro, A.J., Durillo, J.J., García-Nieto, J., Coello Coello, C.A., Luna, F., Alba, E.: SMPSO: a new PSO-based meta-heuristic for multi-objective optimization. In: 2009 IEEE Symposium on Computational Intelligence in Multi-criteria Decision-Making (2009)
Kukkonen, S., Lampinen, J.: GDE3: the third evolution step of generalized differential evolution. In: IEEE Congress on Evolutionary Computation (CEC2005) (2005)
Corne, D.W., Jerram, N.R., Knowles, J.D., Oates, M.J.: PESA-II: region-based selection in evolutionary multi-objective optimization. In: GECCO-2001 (2001)
Eskandari, H., Geiger, C.D., Lamont, G.B.: FastPGA: a dynamic population sizing approach for solving expensive multi-objective optimization problems. In: 4th International Conference on Evolutionary Multi-Criterion Optimization (2007)
Sierra, M.R., Coello Coello, C.A.: Improving PSO-based multi-objective optimization using crowding, mutation and epsilon-dominance. In: EMO (2005)
Branke, J., Schmeck, H., Deb, K., Reddy, S.M.: Parallelizing multi-objective evolutionary algorithms: cone separation. In: Proceedings of the 2004 Congress on Evolutionary Computation (2004)
Vrenios, A.: Parallel programming in C with MPI and OpenMP (Book Review). IEEE Distrib. Syst. Online 5(1), 7.1–7.3 (2004)
MPI, A Message-Passing Interface Standard. Message Passing Interface Forum, version 2.1 (2008)
Thies, W., Karczmarek, M., Amarasinghe, S.: StreamIt: a language for streaming applications. In: 11th International Conference on Compiler Construction (2002)
Munshi, A.: The OpenCL Specification version 1.0. Khronos OpenCL Working Group (2009)
Coppola, M., Locatelli, R., Maruccia, G., Pieralisi, L., Scandurraa, A.: Spidergon: a novel on-chip communication network. In: Proceedings of the International Symposium on System-on-Chip (2004)
Ye, T.T., Benini, L., De Micheli, G.: Packetized on-chip interconnect communication analysis for MPSoC. In: DATE (2003)
Hu, J., Marculescu, R.: Energy-aware mapping for tile-based NoC architectures under performance constraints. In: ASP-DAC (2003)
Hu, J., Marculescu, R.: Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In: DATE (2004)
Dick, R.P., Rhodes, D.L., Wolf, W.: TGFF: task graphs for free. In: Workshop on Hardware/Software Codesign (1998)
Marcon, C., Calazans, N., Moraes, F., Susin, A., Reis, I., Hessel, F.: Exploring NoC mapping strategies: an energy and timing aware technique. In: DATE (2005)
Bourduas, S., Chan, H., Zilic, Z.: Blocking-aware task assignment for wormhole routed network-on-chip. In: MWSCAS/NEWCAS (2007)
Murali, S., Coenen, M., Radulescu, A., Goossens, K., De Micheli, G.: A methodology for mapping multiple use-cases onto networks on chips. In: DATE (2006)
Murali, S., Coenen, M., Radulescu, A., Goossens, K., De Micheli, G.: Mapping and configuration methods for multi-use-case networks on chips. In: ASP-DAC (2006)
Thiele, L., Bacivarov, I., Haid, W., Huang, K.: Mapping applications to tiled multiprocessor embedded systems. In: Application of Concurrency to System Design (2007)
Zhou, W., Zhang, Y., Mao, Z.: Pareto based multi-objective mapping IP cores onto NoC architectures. In: Circuits and Systems, APCCAS (2006)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer Science+Business Media B.V.
About this chapter
Cite this chapter
Bouchebaba, Y., Paulin, P., Nicolescu, G. (2012). MpAssign: A Framework for Solving the Many-Core Platform Mapping Problem. In: Nicolescu, G., O'Connor, I., Piguet, C. (eds) Design Technology for Heterogeneous Embedded Systems. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1125-9_10
Download citation
DOI: https://doi.org/10.1007/978-94-007-1125-9_10
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-007-1124-2
Online ISBN: 978-94-007-1125-9
eBook Packages: EngineeringEngineering (R0)