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Semiconductors

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Materials Chemistry

Abstract

Without question, semiconductors represent the most utilized and under-appreciated material in our society. From our alarm clocks that wake us up in the morning, to our vehicles that bring us home from work each day, semiconductor-based computer chips impact virtually every part of our lives. This chapter will describe the types and properties of semiconductors, and applications such as integrated circuits (chips), light-emitting diodes (LEDs), thermoelectrics, and photovoltaics. Thin-film deposition techniques such as chemical vapor deposition and atomic layer deposition are also described, as well as next-generation patterning techniques such as ‘soft lithography’

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Notes

  1. 1.

    http://ece-www.colorado.edu/~bart/book/book/chapter2/ch2_8.htm

  2. 2.

    For a thorough discussion of the complex threefold non-degeneracy of valence band edges, characterized by heavy hole and light hole bands degenerate at Γ, and a split-off band separated by the magnitude of spin-orbit interaction, see: Kittel, C. Introduction to Solid State Physics, 8th ed., Wiley: New York, 2005. Another useful website resource is: http://mems.caltech.edu/courses/EE40%20Web%20Files/Supplements/01_Effective_Mass.pdf

  3. 3.

    For instance, see:

    (a) Matsui, H.; Terashima, K.; Sato, T.; Takahashi, T.; Wang, S. -C.; Yang, H. -B.; Ding, H.; Uefiji, T.; Yamada, K. Phys. Rev. Lett. 2005, 94, 047005.

    (b) Raj, S.; Hashimoto, D.; Matsui, H.; Souma, S.; Sato, T.; Takahashi, T.; Sarma, D. D.; Mahadevan, P.; Oishi, S. Phys. Rev. Lett. 2006, 96, 147603.

  4. 4.

    Hemlock Semiconductor homepage: http://www.hscpoly.com

  5. 5.

    For example, see:

    (a) Sanjurjo, A. U.S. Patent 5006317.

    (b) Yoon, P.; Song, Y. U.S. Patent 4786477.

    (c) Boone, J. E.; Owens, D. W.; Farritor, R. E.; Blank, W. D. U.S. Patent 4806317.

  6. 6.

    Note: homoepitaxial growth refers to growing a film onto an atomically-flat substrate, wherein both film and substrate are compositionally equivalent. In contrast, heteroepitaxial growth would refer to growing a thin film of different composition onto a substrate (e.g., GaAs thin film on Si). Such film growth occurs usually by vapor-phase techniques, which facilitates exact lattice matching of the crystal orientation and spacing of the growing thin film with the underlying substrate.

  7. 7.

    Note: the solar market has been growing at a rate of 40%/year in recent years, as compared to 4–6%/year for the semiconductor market. For more information on markets and production figures, see: http://www.aiche.org/cep (Aug. 2008 issue).

  8. 8.

    The 65-nm Intel Core 2 Duo chip contained 290 million transistors, whereas its 45-nm successor contains 410 million transistors. In comparison, various multi-core processors have been released in 2010 that feature over 1 billion transistors (http://en.wikipedia.org/wiki/Microprocessor_chronology): IBM’s new 45-nm POWER7 processor (567 mm2) features 1.2 billion transistors; in contrast, the next generation of Intel Itanium processors (“Tukwila” – 699 mm2) is the first to feature over 2 billion transistors for a microprocessor chip. The latest graphics processing unit (GPU – NVIDIA GF100) contains over 3 billion transistors. It should be noted that flash-memory chips have long featured over 1 billion transistors. Since 2005, 8 GB memory chips (146 mm2) have featured over 4 billion transistors, and the latest 32 GB SD cards contain over 100 billion transistors! For an interesting website that provides an updated timeline for PC developments, see: http://www.willus.com/archive/timeline.shtml.

  9. 9.

    Imre, A.; Csaba, G.; Ji, L.; Orlov, A.; Bernstein, G. H.; Porod, W. Science 2006, 311, 205.

  10. 10.

    Note: though the current should, in theory, be zero for a reverse-bias diode, there will still be a very small number of electrons/holes with enough energy to overcome the large junction potential, resulting in a very small current.

  11. 11.

    Note: whereas it is easy to conceptualize the uphill movement of electrons due to an applied voltage that exceeds the junction potential, it is not as straight-forward to rationalize hole migration. That is, they will move downhill from p–n regions during forward bias. A picture that may help visualize this is to think of holes as helium-filled balloons that are adhered to a ceiling. Energy would be required in order to pull them down; having a larger balloon with more helium would require even more energy (analogous to reverse-bias), whereas a small balloon would be easier to pull down (foward bias).

  12. 12.

    (a) ftp://download.intel.com/research/silicon/Chau-paper-IEEE-0403.pdf

    (b) ftp://download.intel.com/research/silicon/tri-gate-transistor-conference-paper-0603.pdf

    (c) Landgraf, E.; Rosner, W.; Stadele, M.; Dreeskornfeld, L.; Hartwich, J.; Hofmann, F.; Kretz, J.; Lutz, T.; Luyken, R. J.; Schulz, T.; Specht, M.; Risch, L. Solid-State Electron. 2006, 50, 38.

  13. 13.

    For a press release, see: http://www.rochester.edu/news/show.php?id=2585

  14. 14.

    (a) http://www.soiconsortium.org/pdf/Consortium_9april09_final.pdf

    (b) http://www.advancedsubstratenews.com/

  15. 15.

    For instance, see:

    (a) Jones, A. C. et al. J. Mater. Chem., 2004, 14, 3101

    (b) Musgrave, C.; Gordon, R. G. Future Fab International 2005, 18, 126.

    (c) Vincenzini, P.; Marletta, G. Adv. Sci. Technol. 2006, 51, 156.

  16. 16.

    http://www.thompson.ece.ufl.edu/Fall2008/intel%20TED-01347396.pdf

  17. 17.

    (a) Sadana, D. K.; Current, M. “Fabrication of Silicon-on-Insulator (SOI) Wafers Using Ion Implantation”, in Ion Implantation Science and Technology, Ziegler, J. F. ed., Edgewater: Ion Implantation Technology Co., 2000.

    (b) Colinge, J. P. Silicon-on-Insulator Technology: Materials to VLSI, 2nd ed., Dordrecht: Kluwer Academic Publishers, 1997.

    (c) http://www.ibis.com – Ibis Technology Corporation, Danvers, MA, USA.

    (d) http://www.chips.ibm.com/bluelogic

    (e) Marshall, A.; Natarajan, S. SOI Design: Analog, Memory, and Digital Techniques, Boston: Kluwer Academic Publishers, 2002.

  18. 18.

    An issue of the MRS Bulletin was recently devoted to scaling future CMOS logic devices with Ge and III-V materials: MRS Bull. 2009, 34, 485.

  19. 19.

    (a) Nihei, R.; Usami, N.; Nakajima, K. Jpn. J. Appl. Phys. 2009, 48, 115507, and references therein.

    (b) Jankovic, N. D.; O'Neill, A. Semicond. Sci. Technol. 2003, 18, 901.

  20. 20.

    Plummer, J. D.; Deal, M. D.; Griffin, P. B. Silicon VLSI Technology: Fundamentals, Practice, and Modeling, Prentice Hall: New Jersey, 2000.

  21. 21.

    A detailed video of the Si(111) 7 × 7 reconstruction may be found at: http://www.vimeo.com/1086112

  22. 22.

    For more details, see:

    (a) http://www.chem.qmul.ac.uk/surfaces/scc/

    (b) http://www.cem.msu.edu/%7Ecem924sg/Topic05.pdf

  23. 23.

    Note: even though single-crystal Si is used as the substrate, the lattice spacings of SiO2 are much greater than Si (5.431 Å).

  24. 24.

    Hess, D. W. Proc. Electrochem. Soc. 96(1), 143.

  25. 25.

    Kriegler, R. J. Semiconductor Silicon 1973, The Electrochemical Society: Princeton, NJ, 1973.

  26. 26.

    Note: the majority of ICs utilize a Si(100) substrate, largely due to the desirable electrical properties of the Si(100)/SiO2 interface.

  27. 27.

    A comprehensive users guide to photolithography may be found online at:

    http://www.ee.washington.edu/research/microtech/cam/PROCESSES/PDF%20FILES/Photolithography.pdf

  28. 28.

    Note: for GaAs substrates, primers such as xylene or trichlorobenzene are used, as GaAs is already a polar surface.

  29. 29.

    Note: masks are either comprised of soda-lime glass (coated with either a photographic emulsion, Fe2O3, or Cr films), or quartz (with a Cr film). Due to the absorption of UV light by glass, the latter is required for deep UV (DUV) photolithography. Masks may be classified as either “light-field” or “dark-field”; whereas the former is mostly clear with opaque patterns, the latter is an opaque mask, with transparent features.

  30. 30.

    For example:

    (a) Nonogaki, S. Polymer J. 1987, 19, 99.

    (b) Liu, H. -H.; Chen, W. -T.; Wu, F. -C. J. Polym. Res. 2002, 9, 251.

  31. 31.

    The use of double- and triple-patterning has extended the 193-nm photolithography timeline beyond that originally anticipated. For more details on this technology,

    see: Wu, B.; Singh, A. K. Extreme Ultraviolet Lithography, McGraw-Hill: New York, 2009 (page 5 of the Introduction has a lithography roadmap for the extension of 193-nm photolithography, and EUV not likely being instituted until the 22 or 16 nm node (ca. 2015+).

  32. 32.

    For more details regarding EUV, see: Hutcheson, G. D. et al. Scientific American 2004, 290, 76.

  33. 33.

    For information regarding EUV mask design may be found online at:

    http://www.sematech.org/meetings/archives/litho/euvl/20030930/presentations/2C%20Shoki%20EUV%20Symp.pdf

  34. 34.

    Hiroshi, I. Adv. Polym. Sci. 2005, 172, 37, and references therein.

  35. 35.

    (a) http://people.ccmr.cornell.edu/~cober/MiniPresentations/PAG_RBSPC.pdf

    (b) Kim, K. -M.; Ayothi, R.; Ober, C. K. Polym. Bull. 2005, 55, 333.

  36. 36.

    For instance, see:

    (a) Dai, J.; Ober, C. K.; Wang, L.; Cerrina, F.; Nealey, P. F. Proc. SPIE – Int. Soc. Opt. Eng. 2002, 4690, 1193.

    (b) Kessel, C. R.; Boardman, L. D.; Rhyner, S. J.; Cobb, J. L.; Henderson, C. C.; Rao, V.; Okoroanyanwu, U. Proc. SPIE – Int. Soc. Opt. Eng. 1999, 3678, 214.

    (c) Bratton, D.; Yang, D.; Dai, J.; Ober, C. K. Polym. Adv. Technol. 2006, 17, 94, and references therein.

  37. 37.

    Note: the depth of focus (DOF = λ/(NA)2) is also paramount toward resolution, as wafers are not atomically flat. Though it may be possible to adjust the wavelength and NA to achieve better resolution, the depth of field will decrease, making it difficult to define features simultaneously at the top and bottom surfaces. Consequently, chemical mechanical polishing (CMP) is used to planarize the wafer prior to high-resolution photolithography, and as thin a layer as possible of photoresist is applied to the wafer.

  38. 38.

    Article may be accessed online at: http://turroserver.chem.columbia.edu/PDF_db/publications_801_850/NJT849.pdf

  39. 39.

    There are two methods used to remove the patterned material. Etching is where the photoresist is developed on top of the deposited layer. The underlying material is then removed by etching through openings in the mask. In contrast, lift-off is used when the material is deposited on top of the developed photoresist. The material is then lifted off when the resist is removed. For a nice summary of wet/dry etching, as well as etching vs. lift-off, see: http://www.mrsec.harvard.edu/education/ap298r2004/Erli%20chen%20Fabrication%20III%20-%20Etching.pdf

  40. 40.

    Note: a plasma is considered the fourth class of matter, in addition to solids, liquids, and gases. A plasma contains a mixture of ground-state and excited-state atoms, as well as ions.

  41. 41.

    C. J. Mogab, A. C. Adams, and D. L. Flamm, J. Appl. Phys. 1978, 49(7), 3796.

  42. 42.

    As its name applies, chemical mechanical polishing/planarization utilizes a hybrid of chemical and mechanical forces to yield a flat surface. It should be noted that using mechanical force alone (e.g., grinding) would successfully planarize a surface; however, this would cause too much surface degradation. For more information about this process, see: http://maltiel-consulting.com/CMP-Chemical-mechanical_planarization_maltiel_semiconductor.pdf

  43. 43.

    In contrast to crystalline Si, polysilicon is formed at much lower temperatures (150–350°C) and is comprised of individual grains of dimensions between ca. 10 nm and 1 μm. The electrical conductivity of a polysilicon gate may be altered by doping or increased by depositing a surface coating of a metal (e.g., W) or silicide (e.g., WSi2). It should be noted that the 32-nm Intel chips now feature a metallic gate that, in combination with a high-κ dielectric gate insulator (HfOx), leads to a 20% +increase in transistor switching speeds and a 100-fold decrease in the gate oxide leakage current(http://www.intel.com/technology/silicon/high-k.htm). For more details regarding the future scaling of CMOS transistors past 32 nm, see: http://download.intel.com/pressroom/pdf/kkuhn/Kuhn_Advanced_Semiconductor_Manufacturing_Conference_keynote_July_13_2010_text.pdf

  44. 44.

    It should be noted that for memory chips and removable flash drives, a gate stack structure known as SONOS (polysilicon/SiO2/Si3N4/SiO2/Si substrate) is typically used. The device is programmed by applying a voltage to the gate to inject charge into the conduction band of the Si3N4 layer, resulting in a change in the threshold voltage. When the voltage is removed, the charge remains trapped within the Si3N4 layer. High-κ metal oxides such as ZrO2 and HfO2 are also capable of trapping injected electrons; if these replace Si3N4, the memory device is known as SOMOS (where M refers to metal oxide). The charge-trapping ability is most pronounced for materials that exhibit a high dielectric constant (i.e., are nonconducting and polarizable), and have sufficient density to prevent tunneling to surrounding layers. To erase the device, a reverse bias voltage is applied that removes the trapped charge from the Si3N4 region. Typically, the SiO2 adjacent to the polysilicon gate is thicker than the SiO2/Si interface, resulting in charge injection occurring through the bottom SiO2 layer.

  45. 45.

    This is typically performed through use of templates that are sacrificially removed following film deposition. For example, see:

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  46. 46.

    For an animated website to illustrate the DC-diode and magnetron sputtering processes, see: http://www.ajaint.com/whatis.htm

  47. 47.

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    (c) Chen, R. S.; Huang, Y. S.; Liang, Y. M.; Tsai, D. S.; Tiong, K. K. J. Alloys Compd. 2004, 383, 273.

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  49. 49.

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  50. 50.

    For a thorough description of kinetic and mass-transport mechanisms involved in CVD, as well as dependent variables, see: Pierson, H. O. Handbook of Chemical Vapor Deposition, 2nd ed., William Andrew: Norwich, NY, 1999.

  51. 51.

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    http://nextbigfuture.com/2009/06/euv-lithography-could-be-commercial.html – a recent press release indicates that EUV lithography will likely be implemented for high volume production by 2012–2014, with feature sizes well below 32 nm.

  64. 64.

    Note: in order to reduce the adhesion between a polymeric mold and a silicon/quartz master, the master surface is typically modified with a fluorosilane (e.g., CF3(CF2)6(CH2)2SiCl3(g)). In addition, the final removal of the mold may also be carried out in the presence of a liquid with a low viscosity such as methanol (solvent-assisted micromolding (SAMIM)).

  65. 65.

    For a nice survey of the benefits for (nano)imprint lithography relative to photolithography, see: http://www.molecularimprints.com/NewsEvents/tech_articles/new_articles/SPIE_07_MMS.pdf

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    A recent thorough review of nanofabrication using both hard and soft molds, as well as other forms of soft lithography, see: Gates, B. D.; Xu, Q.; Stewart, M.; Ryan, D.; Willson, C. G.; Whitesides, G. M. Chem. Rev. 2005, 105, 1171; for instance, CDs are made by imprinting patterns from Ni masters in polycarbonate (a) J. S. Winslow, IEEE Trans. Consumer Electron. 1976 (Nov.), 318; holograms are made by imprinting patterns from a fused quartz master in SURPHEX photopolymer (F. P. Shvartsman

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    Note: we will discuss the operating principle of atomic force microscopy (AFM) and other scanning force microscopies in more detail in Chap. 7. At this point, simply think of this technique as analogous to an antiquated record player, in which the needle gently touches the surface of the record to produce music. Similarly, the AFM tip either gently taps, or hovers immediately above, the surface of a planar substrate to reveal its surface topography.

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    A very nice review of the various DPN methodologies is provided by: Ozin, G. A.; Arsenault, A. C. Nanochemistry: A Chemical Approach to Nanomaterials, 2nd ed. RSC: Cambridge, UK, 2009, pp. 173–204.

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Further Reading

  1. Kasap, S. O. Principles of Electronic Materials and Devices, 2nd ed., Prentice Hall: New Jersey, 2002.

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  2. Plummer, J. D.; Deal, M. D.; Griffin, P. B. Silicon VLSI Technology: Fundamentals, Practice, and Modeling, Prentice Hall: New Jersey, 2000.

    Google Scholar 

  3. http://www.ee.byu.edu/cleanroom/semiconductor_properties.phtml; contains a variety of useful semiconductor information, provided by Brigham Young University, Dept. of Electrical and Computer Engineering.

  4. Physics and Chemistry of III–V Compound Semiconductor Interfaces, Wilmsen, C. ed., Springer: New York, 1985.

    Google Scholar 

  5. Misra, A.; Hogan, J. D.; Chorush, R. A. Handbook of Chemicals and Gases for the Semiconductor Industry, Wiley: New York, 2002.

    Book  Google Scholar 

  6. Moss, S. J.; Ledwith, A. The Chemistry of the Semiconductor Industry, Chapman and Hall: New York, 1987.

    Google Scholar 

  7. Turley, J. The Essential Guide to Semiconductors, Prentice Hall: New Jersey, 2003.

    Google Scholar 

  8. Pierret, R. F. Semiconductor Fundamentals, Volume I, 2nd ed., Prentice Hall: New Jersey, 1988.

    Google Scholar 

  9. Streetman, B.; Banerjee, S. Solid State Electronic Devices, 5th ed., Prentice Hall: New Jersey, 1999.

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  10. Hamers, R. J.; Wang, Y. “Atomically-Resolved Studies of the Chemistry and Bonding at Silicon Surfaces” Chem. Rev. 1996, 96, 1261.

    Article  Google Scholar 

  11. Waltenburg, H. N.; Yates, J. T. “Surface Chemistry of Silicon” Chem. Rev. 1995, 95, 1589.

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  12. Recent reviews of high-κ dielectric materials: (a) Locquet, J. -P.; Marchiori, C.; Sousa, M.; Fompeyrine, J.; Seo, J. W. J. Appl. Phys. 2006, 100, 051610; (b) Robertson, J. Rep. Prog. Phys. 2006, 69, 327.

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  13. Announcement by Intel regarding the 45 nm technology scheduled for 2007: http://download.intel.com/technology/silicon/Press_45nm_106.pdf

  14. http://smithsonianchips.si.edu/index2.htm

  15. Pierson, H. O. Handbook of CVD, 2nd ed., Noyes Publications, 1999.

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    Bradley D. Fahlman

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Fahlman, B.D. (2011). Semiconductors. In: Materials Chemistry. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-0693-4_4

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