Abstract
This chapter deals with the design of DS modulators for wireless applications. Two case studies are presented to discuss general design issues and to give insights into the possibilities that exist for solving contemporary challenges with time-domain processing techniques. The first architecture employs a time-to-digital converter based on pulse-width. Its time-based single-level DAC achieves linear multi-bit feedback, leading to the DS modulator’s dynamic range of 68 dB. The second architecture employs a 7-phase 400 MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and DAC. Fabricated in a 0.18 μm CMOS technology, the 5th-order modulator achieves a peak SNDR of 67.7 dB in 25 MHz bandwidth, consumes 48 mW, and occupies a die area of 2.6 mm2. This modulator has a measured SFDR of 78 dB and in-band IM3 under −72 dB at −2dBFS.
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Acknowledgements
The authors would like to recognize that these ADCs were developed with the collaboration of Prof. E. Sanchez-Sinencio, M. Elsayed, E. Pankratz, Y. C. Lo, V. Gadde, and V. Periasamy. The authors appreciate the chip fabrications sponsored by Texas Instruments and Jazz Semiconductor.
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Silva-Martinez, J., Lu, CY., Onabajo, M., Silva-Rivas, F., Dhanasekaran, V., Gambhir, M. (2011). Wideband Continuous-Time Multi-Bit Delta-Sigma ADCs. In: Casier, H., Steyaert, M., van Roermund, A. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-0391-9_11
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DOI: https://doi.org/10.1007/978-94-007-0391-9_11
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