A 14 Bit Quad Core Flexible 180 nm DAC Platform

Abstract

This chapter presents a flexible DAC design that features 4.12 bit sub-DAC cores and it is designed in 180 nm CMOS technology. The test chip has a simple pre-processor in the form of an externally controlled de-multiplexer to distribute the digital sub-DAC input words w _i (nT ), i = 1, 2, 3, 4. The analog post-processing is an off-chip summation of the sub-DAC output currents. For a SoC co-integration, the design of the sub-DAC unit needs to be area efficient, since the production cost of the DAC platform is added to the price of the whole SoC. Therefore, a large binary LSB portion is chosen for the segmentation of the sub-DAC unit. Its architecture features 8 LSB binary bits and 4 MSB unary bits (15 unary currents). To save furthermore silicon area, the sub-DAC unit has relaxed design specifications of about 9–10 bits intrinsic linearity. The smart op-modes of the flexible DAC architecture and a built-in self-calibration apparatus can improve the DAC static linearity to state-of-the-art levels, while the occupied silicon area of the flexible DAC platform is one of the smallest reported in the literature. It is 0.2 mm² per 12 bit sub-DAC unit, i.e. 0.8 mm² for the whole flexible 14 bit DAC platform.