Two Self-Calibrating DAC Designs

Abstract

This chapter presents the implementation and measurement results of two DAC test-chip implementations in 250 nm and 180 nm standard CMOS processes. The chapter considers the test-chips primarily from the calibration point of view. The measurement results show that the practical limit of the presented calibration easily exceeds the 14 bit level. The 250 nm and 180 nm test chips feature fully-integrated calibration engines. The first test-chip is a 12 bit 250 nm current-steering DAC with unary currents calibration. The second test-chip is a flexible 12 bit quad-core 180 nm current-steering DAC with both binary and unary currents calibration. This is the first reported DAC implementation that calibrates the errors of all its current sources.