New Redundant Decoder Concept

Abstract

The following text describes a new architecture for binary-to-thermometer decoders used in segmented D/A converters to decode the input binary bits into unary bits. To efficiently improve basic DAC characteristics, the architecture features redundant output unary codes. The main concept offers two modes of operation. Each mode generates a different unary output, i.e. a different switching sequence for the DAC (MSB) unary analog elements. The correlation between both switching sequences is low due to the “geometrical” properties of the decoder. This results in two different transfer characteristics of the whole DAC for the same mismatch errors of its elements. After on-chip or off-chip measurements, the more linear transfer characteristic can be selected. Alternatively, the two switching sequences can be dynamically averaged, similarly to DEM correction methods. In either way, chip yield is improved and the design requirements can be relaxed. Ultimately, the advantages introduced by the proposed decoder will lead to cheaper and smaller D/A Converters.