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A One-Way Link Transceiver Design

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Part of the book series: Analog Circuits and Signal Processing ((ACSP))

Abstract

This chapter describes the design and the implementation of an ultra-low power transmitter for a one-way link WSN scenario. The first part of the chapter starts from an in-depth description of the radio architecture and continues with a detailed description of a novel frequency pre-distortion transmitter based on a direct modulation of the VCO. The transistor level implementation of the transmitter building blocks is discussed in detail and the various trade-offs in the transmitter design are analyzed. The second part of the chapter focuses on the algorithms (synchronization and demodulation) required at the RG side to correctly receive the incoming data. Finally, implementation details and measurement data are given, showing that a fast frequency-hopping TX radio with a −5 dBm output power can be designed within a 4.4 mW power budget. A link between the RG and the ultra-low power TX node showed a raw BER smaller than 1.1% at 8 meters distance and non-line-of-sight conditions. This allows to sustain a link quality of service in line with the requirements of WSNs.

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Notes

  1. 1.

    It should be noticed that the extra hardware required for the FLL based coarse calibration respect to the EEPROM based factory calibration is the FD and the digital dividers (not shown in Fig. 4.2).

  2. 2.

    In the implemented case only a ROM is used because the calibrated coarse varactor voltage is stored on the coarse varactor capacitance and the coarse DAC is switched off after coarse calibration is performed.

  3. 3.

    The error probability of a non-coherent BFSK modulated signal is given by \(\frac{1}{2}e^{-\frac{E_{\mathrm{b}}}{2N_{0}}}\). Considering a 0.1% initial BER, a 0.5 dB degradation in the phase noise translates into a 0.5 dB degradation in the SNR at the demodulator input and therefore, into a BER close to 0.2%.

  4. 4.

    Given 64 channels and a 150 kHz separation between adjacent channels, the minimum and maximum channel frequencies are 910.35 MHz and 919.65 MHz, respectively.

  5. 5.

    For an 11 bit DAC 1 mV corresponds to 2 LSB and for a 12 bit DAC it corresponds to 4 LSB.

  6. 6.

    With raw BER, in this book, we mean the BER when no error correction code is applied.

  7. 7.

    Supposing the errors in a packet are uniformly distributed is a worst case scenario especially for burst based communications. The formula used to derive the PER starting from the channel BER is, in this simplified case, PER=1−(1−BER)P where P is the packet length.

  8. 8.

    Note that the tuning voltage equals 1.8 V+V var, with V var the voltage over the varactor, because, when the tuning voltage is 0 V, there is already 1.8 V at the cathode.

  9. 9.

    Some margin is required, compared to the earlier mentioned −25 dBm (see Table 4.2), in order to account for cable and board losses in a real prototype.

  10. 10.

    The optimal power consumption in terms of transmitter efficiency is obtained when all the power used in the RF section is effectively radiated from the antenna.

  11. 11.

    Considering the channel allocation mentioned in Sect. 4.2, the maximum offset the algorithm needs to recover is around 9.3 MHz. The system data rate, on the contrary, is in the order of few kilobit per second.

  12. 12.

    This does not include the last iteration required to confirm the frequency acquisition, which takes around 230 μs.

  13. 13.

    If we suppose that for 50% of the symbol period we transmit the offset information and for the remaining 50% we transmit the effective data, the effective data-rate is halved.

  14. 14.

    Compared to two coils.

  15. 15.

    Only 12 out of 16 bits are used and after the 12 bits are loaded, a reset signal is used to reset the two registers for the next hopping bin synthesis.

  16. 16.

    The PCB for the LC-divider based prototype is very similar and therefore, it has not been shown in this book.

  17. 17.

    The phase noise specification in Table 4.2 already includes a 3 dB margin to account for implementation losses. Therefore, it is possible to state that the −102 dBc/Hz exceeds by 2 dB the minimum phase noise requirement (see Sect. 4.2.3).

  18. 18.

    The oscillator frequency in Fig. 4.62 is an alias of the synthesized frequency due to the sampling rate used in the measurement setup. Indeed, the 25 Ms/s rate is lower than required by the Nyquist theorem.

  19. 19.

    Indeed, because all the channels are addressed in a sequential way, the DAC output should look like a voltage ramp. Due to the frequency pre-distortion, it is clearly visible in Fig. 4.63 that the DAC output has a curved shape instead of a ramp like shape.

  20. 20.

    In practice this is a worst case condition because the system could benefit from a much smaller than designed frequency diversity.

  21. 21.

    In this book the transmitter efficiency is defined as the ratio between the radiated power and the overall transmitter power consumption.

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Lopelli, E., van der Tang, J., van Roermund, A. (2011). A One-Way Link Transceiver Design. In: Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-0183-0_4

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  • DOI: https://doi.org/10.1007/978-94-007-0183-0_4

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-007-0182-3

  • Online ISBN: 978-94-007-0183-0

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