Abstract
Static noise margins have been traditionally used to characterize the stability of static memories such as SRAMs. Continuing technology scaling has significantly shrunk the stability margins of static memories. Due to their inability in capturing nonlinear cell dynamics, static noise margins become increasingly inappropriate for state-of-the-art SRAMs with shrinking access time and/or advanced dynamic read-write-assist circuits. Based upon understandings derived from rigorous nonlinear system theory, we define new static memory dynamic noise margin concepts. These new metrics not only capture key nonlinear dynamical stability properties but also provide valuable design insights. Furthermore, we discuss advanced numerical simulation techniques that are appropriate for analyzing dynamic stability with good robustness and efficiency.
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References
J. Lohstroh, E. Seevinck, and J. D. Groot. Worst-case static noise margin criteria for logic circuits and their mathematical equivalence. In J. of Solid-State Circuits, (IEEE, Dec 1983), pp. 803–806.
E. Seevinck, F. J. List, and J. Lohstroh. Static-noise margin analysis of MOS SRAM cells. In J. of Solid-State Circuits, (IEEE, Oct 1987), pp. 748–754.
J. Zaborszky, G. M. Huang, B. Zheng, and T. C. Leung. Static-noise margin analysis of MOS SRAM cells. In Trans. Automatic Control, (IEEE, Jan 1988), pp. 4–15.
C. W. Gear and I. G. Kevrekidis. Telescopic projective methods for parabolic differential equations. In Physics Letter A, (vol. 187, 2003), pp. 95–109.
S. Wiggins. in Introduction to Applied Nonlinear Dynamical Systems and Chaos, (Springer, 2003).
C. W. Gear and I. G. Kevrekidis. Computing in the past with forward integration. In Physics Letter A, (vol. 321, 2004), pp. 335–343.
M. Khellah, Y. Ye, N. S. Kim, D. Somasekhar, G. Pandya, A. Farhang, K. Zhang, C. Webb and V. De. Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65 nm CMOS designs. In Digest of Technical Papers, Symp. on VLSI Circuits, (IEEE, June 2006), pp. 9–10.
H. Pilo et al. An SRAM design in 65 nm and 45 nm technology nodes featuring read and write-assist circuits to expand operating voltage. In Digest of Technical Papers, Symp. on VLSI Circuits, (IEEE, June 2006), pp. 15–16.
G. M. Huang, W. Dong, Y. Ho, and P. Li. Tracing SRAM separatrix for dynamic noise margin analysis under device mismatch. In Int. Behavioral Modeling and Simulation Conf., (IEEE, 2007), pp. 6–10.
W. Dong, P. Li and G. M. Huang. SRAM dynamic stability: theory, variability and analysis. In Proc. of Int. Conf. on Computer-Aided Design, (IEEE/ACM, 2008), pp. 378–385.
W. Dong and P. Li. Final-value ODEs: stable numerical integration and its application to parallel circuit analysis. In Proc. of Int. Conf. on Computer-Aided Design, (IEEE/ACM, 2009), pp. 403–409.
Y. Zhang, P. Li and Garng M. Huang. Separatrices in high-dimensional state space: system-theoretical tangent computation and application to SRAM dynamic stability analysis. In Proc. of Design Automation Conf., (IEEE/ACM, 2010), pp. 567–572.
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Li, P., Dong, W., Huang, G.M. (2011). Dynamic Stability of Static Memories: Concepts and Advanced Numerical Analysis Techniques. In: Li, P., Silveira, L., Feldmann, P. (eds) Simulation and Verification of Electronic and Biological Systems. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-0149-6_5
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DOI: https://doi.org/10.1007/978-94-007-0149-6_5
Publisher Name: Springer, Dordrecht
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