Skip to main content

Approximate Multiplication and Division for Arithmetic Data Value Speculation in a RISC Processor

  • Chapter
Algorithm-Architecture Matching for Signal and Image Processing

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 73))

Abstract

Arithmetic data value speculation increases the throughput of a processor by using approximation to speculatively issue instructions dependent on an arithmetic result. This chapter describes new approximate multipliers and dividers. The performance advantage of these units is demonstrated in a practical context through simulation of a 32 bit RISC processor, modified to use these approximate units for arithmetic data value speculation. Instruction throughput improved by more than 15% for some media benchmarks.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Abbreviations

n :

number of input bits to a counter

m :

number of output bits from a counter

z :

dividend

d :

divisor

q :

exact quotient after division q=z/d

r :

remainder after division

\(\tilde{d}\) :

approximate divisor

q i :

quotient after round i

r i :

remainder after round i

t :

maximum number of division rounds

f :

number of fractional bits maintained in q i

References

  1. Akgul B, Chakrapani L, Korkmaz P, Palem K (2006) Probabilistic CMOS technology: a survey and future directions. In: 2006 IFIP international conference on very large scale integration, pp 1–6

    Google Scholar 

  2. Artisan Components, Inc., Sunnyvale, CA, USA (2002) TSMC 0.18 μm Process 1.8 Volt SAGE-X™Standard Cell Library Databook

    Google Scholar 

  3. Baugh CR, Wooley BA (1973) A two’s complement parallel array multiplication algorithm. IEEE Trans Comput C-22:1045–1047. Reprinted in Swartzlander EE, Computer arithmetic, vol 1. IEEE Computer Society Press Tutorial, Los Alamitos, CA, 1990

    Article  Google Scholar 

  4. Burger D, Austin TM (1997) The SimpleScalar tool set version 2.0. SIGARCH Comput Archit News 25(3):13–25

    Article  Google Scholar 

  5. Burger D, Goodman JR (2004) Billion-transistor architectures: there and back again. IEEE Comput Mag 37(3):22–28

    Article  Google Scholar 

  6. Das S, Roberts D, Lee S, Pant S, Blaauw D, Austin T, Flautner K, Mudge T (2006) A self-tuning DVS processor using delay-error detection and correction. IEEE J Solid-State Circuits 41(4):792–804

    Article  Google Scholar 

  7. Das S, Tokunaga C, Pant S, Ma WH, Kalaiselvan S, Lai K, Bull D, Blaauw D (2009) RazorII: in situ error detection and correction for PVT and SER tolerance. IEEE J Solid-State Circuits 44(1):32–48

    Article  Google Scholar 

  8. George J, Marr B, Akgul BES, Palem KV (2006) Probabilistic arithmetic and energy efficient embedded signal processing. In: Hong S, Wolf W, Flautner K, Kim T (eds) Proceedings of the 2006 international conference on compilers, architecture, and synthesis for embedded systems, CASES 2006, Seoul, Korea, October 22–25, 2006. ACM, New York, pp 158–168

    Google Scholar 

  9. HP labs: Hp labs: cacti (2008) online: http://www.hpl.hp.com/research/cacti/

  10. Kelly DR, Phillips BJ (2005) Arithmetic data value speculation. Lect Notes Comput Sci (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol 3740. Springer, Singapore, pp 353–366

    Google Scholar 

  11. Kelly DR, Phillips BJ, Al-Sarawi SF (2009) Approximate signed binary integer multipliers for arithmetic data value speculation. In: Proceedings of the conference on design and architectures for signal and image processing (DASIP). Sophia Antipolis, France. http://www.ecsi-association.org/ecsi/dasip/dasip09

  12. Kelly DR, Phillips BJ, Al-Sarawi SF (2009) Approximate unsigned binary integer dividers for arithmetic data value speculation. In: Proceedings of the conference on design and architectures for signal and image processing (DASIP). Sophia Antipolis, France. http://www.ecsi-association.org/ecsi/dasip/dasip09

  13. Kelly DR, Phillips BJ, Al-Sarawi SF (2009) Increasing throughput of a RISC system using arithmetic data value speculation. In: Conference record of the forty-third Asilomar conference on signals, systems, and computers, 2009. IEEE, Pacific Grove

    Google Scholar 

  14. Korkmaz P, Akgul B, Palem K (2008) Energy performance, and probability tradeoffs for energy-efficient probabilistic CMOS circuits. IEEE Trans Circuits Syst I, Regul Pap 55(8):2249–2262

    Article  MathSciNet  Google Scholar 

  15. Lee C, Potkonjak M, Mangione-Smith WH (1997) Mediabench: a tool for evaluating and synthesizing multimedia and communications systems. In: Proceedings of the annual international symposium on microarchitecture. IEEE, Triangle Park, pp 330–335

    Google Scholar 

  16. Li A (2002) An empirical study of the longest carry length in real programs. Master’s thesis. Department of Computer Science, Princeton University

    Google Scholar 

  17. Lipasti MH, Shen JP (1996) Exceeding the dataflow limit via value prediction. In: Proceedings of the 29th annual IEEE/ACM Int. symposium on microarchitecture. IEEE, Washington, pp 226–237

    Chapter  Google Scholar 

  18. Liu T, Lu SL (2000) Performance improvement with circuit level speculation. In: Proceedings of the 33rd annual international symposium on microarchitecture. ACM, New York, pp 348–355

    Google Scholar 

  19. Lu SL (2004) Speeding up processing with approximation circuits. IEEE Comput Mag 37(3):67–73

    Article  Google Scholar 

  20. Oberman SF, Flynn MJ (1997) Design issues in division and other floating-point operations. IEEETC: IEEE Trans Comput 46

    Google Scholar 

  21. Parhami B (2000) Computer arithmetic: algorithms and hardware designs. Oxford University Press, New York

    Google Scholar 

  22. Phillips BJ, Kelly DR, Ng BW (2006) Estimating adders for a low density parity check decoder. In: Proceedings of SPIE—the international society for optical engineering, Proc. SPIE vol 6313. SPIE, Bellingham

    Google Scholar 

  23. Richardson SE (1992) Caching function results: faster arithmetic by avoiding unnecessary computation. Tech. Rep., Mountain View, CA, USA

    Google Scholar 

  24. Tarjan D, Thoziyoor S, Jouppi NP (2006) Cacti 4.0. Tech. Rep. HPL-2006-86, HP Labs. Available online http://www.hpl.hp.com/techreports/2006/HPL-2006-86.html

  25. Wang L, Shanbhag N (2000) Adaptive error-cancellation for low-power digital filtering. In: Conference record of the thirty-fourth Asilomar conference on signals, systems, and computers. IEEE, Pacific Grove

    Google Scholar 

  26. Yang L, Tong Z, Parhi K (2008) Analysis of voltage overscaled computer arithmetics in low power signal processing systems. In: Conference record of the forty-second Asilomar conference on signals, systems, and computers. IEEE, Pacific Grove

    Google Scholar 

Download references

Acknowledgement

The authors would like to thank eResearch SA for their support and resources used to complete the simulations used for this chapter.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Daniel R. Kelly .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media B.V.

About this chapter

Cite this chapter

Kelly, D.R., Phillips, B.J., Al-Sarawi, S. (2011). Approximate Multiplication and Division for Arithmetic Data Value Speculation in a RISC Processor. In: Gogniat, G., Milojevic, D., Morawiec, A., Erdogan, A. (eds) Algorithm-Architecture Matching for Signal and Image Processing. Lecture Notes in Electrical Engineering, vol 73. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9965-5_5

Download citation

  • DOI: https://doi.org/10.1007/978-90-481-9965-5_5

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-9964-8

  • Online ISBN: 978-90-481-9965-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics