Abstract
Arithmetic data value speculation increases the throughput of a processor by using approximation to speculatively issue instructions dependent on an arithmetic result. This chapter describes new approximate multipliers and dividers. The performance advantage of these units is demonstrated in a practical context through simulation of a 32 bit RISC processor, modified to use these approximate units for arithmetic data value speculation. Instruction throughput improved by more than 15% for some media benchmarks.
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Abbreviations
- n :
-
number of input bits to a counter
- m :
-
number of output bits from a counter
- z :
-
dividend
- d :
-
divisor
- q :
-
exact quotient after division q=z/d
- r :
-
remainder after division
- \(\tilde{d}\) :
-
approximate divisor
- q i :
-
quotient after round i
- r i :
-
remainder after round i
- t :
-
maximum number of division rounds
- f :
-
number of fractional bits maintained in q i
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The authors would like to thank eResearch SA for their support and resources used to complete the simulations used for this chapter.
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Kelly, D.R., Phillips, B.J., Al-Sarawi, S. (2011). Approximate Multiplication and Division for Arithmetic Data Value Speculation in a RISC Processor. In: Gogniat, G., Milojevic, D., Morawiec, A., Erdogan, A. (eds) Algorithm-Architecture Matching for Signal and Image Processing. Lecture Notes in Electrical Engineering, vol 73. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9965-5_5
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DOI: https://doi.org/10.1007/978-90-481-9965-5_5
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