Abstract
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. As discussed in Chapter 2, practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification.
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Appendix
Appendix
6.1.1 A.1 Time Mismatch
Let the original sampled data sequence S = [x(t 0 ), x(t 1 ), x(t 2 ), …, x(t m ), …, x(t N ), x(t N+1 ),…] be divided into N subsequences S 0 , S 1 , S 2 , …, S N−1 as follows [133]:
The S n is obtained by uniformly sampling the signal x(t + t n ) at the rate 1/NT. Assume
the original sequence S, can be represented as
Then, the digital spectrum, X(ω), of S can be represented as
Let r n T, n = 0,1,N − 1 be the sampling time offset encountered at the nth sample-hold unit (positive r n means that the nth sample is delayed), and t n real sampling time for nth sample-hold unit,
then (A.4) can be rewritten as
For a given sine wave x(t) = sin(ω in t), the Fourier transform X a (ω) is given by
where δ is unit sample sequence δ[x] = 1 at x = 0, and 0 elsewhere, (A.6) becomes [133]
where
The digital spectrum given by (A.8) has N pairs of line spectra, each pairs centered at the fractional of the sampling frequency, such as f S /N,…,(N−1) f S /N.
Fundamental corresponds to k = 0 while k = 1, …, N − 1 corresponds to the distortion. The signal amplitude is determined by A(0) while the distortion amplitudes are determined by A(n), n = 1, …, N − 1. A(k) is a DFT of the sequence of \( [(1/N){e^{ - j{r_n}2\pi {f_0}/{f_s}}},n = 0,1,2,...,N - 1] \).
Assuming r n 2πf in /f S «1, the magnitude of the sidebands components can be expressed as:
The signal power is A 2 /2 and power density of a spurious due to the time mismatch is expressed as
6.1.2 A.2 Offset Mismatch
The offset mismatch can be modeled by adding a dc level with the input signal that is unique for each S/H unit. For a input signal A sin(ω in t) + d n with n = 0, …, N − 1, the Fourier transform is given by
If no timing error is assumed rn is zero. Substituting previous equation in (A.8),
where
The first term of (A.12) corresponds to the input signal, while the second term corresponds to the distortion caused by channel offset. The distortion is not signal dependent and appears at nf S /N, where n = 0,1, …, N − 1. From previous equation can be seen that the distortion consists of a sum of impulses. Each impulse corresponds to a complex exponential signal in the time domain e jω. The power of the exponential signal is 1. The factors A(k) can be seen as the DFT of the sequence d n /N, n = 0, 1, …, N − 1. Power density of a spurious due to the offset mismatch is expressed as
6.1.3 A.3 Gain Mismatch
To model gain mismatch, magnitude of one of the S/H unit input signals is different. The largest difference occurs at the peaks of the sine wave. The signal is a n sin(ω in t) with n = 0, …, N − 1. The Fourier transform is given by
If no timing error is assumed r n is zero. Substituting previous equation in (A.8),
where
for the gain mismatches in N S/H units with spurious tones at f S /N ± f in , 2f S /N ± f in , …, (N − 1) f S /N ± f in . Power density of a spurious due to the gain mismatch is expressed as
6.1.4 A.4 Bandwidth Mismatch
To model frequency dependent bandwidth mismatch, the S/H Amplifiers are approximated as the ideal one-pole amplifiers. For a one-pole system, A(s) = A 0 /(1 + s/ω 0), the closed loop transfer function is
Recognizing that A 0 β » 1, the previous equation becomes
for β = 1. For a given sine wave x(t) = sin(ω in t), the Fourier transform X a (ω) is given by
and Eq. (A.8) with r n = 0 becomes
where
with f 1 unity-gain frequency and b n bandwidth offset experienced by the nth S/H amplifier with spurious tones at f S /N ± f in , 2f S /N ± f in , …, (N − 1) f S /N ± f in . The signal power is A 2 /2 and power density of a spurious due to the gain-bandwidth mismatch is expressed as
6.1.5 A.5 General Expression
The general expression for spurious-free dynamic range (SFDR) is given by
where the input signal power is defined as P s = A 2 /2.
6.1.6 B.1 Histogram Measurement of ADC Nonlinearities Using Sine Waves
The histogram or output code density is the number of times every individual code has occurred. For an ideal A/D converter with a full scale ramp input and random sampling, an equal number of codes is expected in each bin. The number of counts in the ith bin H(i) divided by the total number of samples N t , is the width of the bin as a fraction of full scale. By compiling a cumulative histogram, the cumulative bin widths are the transition levels.
The use of sine wave histogram tests for the determination of the nonlinearities of analog-to-digital converters (ADCs) has become quite common and is described in [336, 414]. When a ramp or triangle wave is used for histogram tests (as in [433]), additive noise has no effect on the results; however, due to the distortion or nonlinearity in the ramp, it is difficult to guarantee the accuracy.
For a differential nonlinearity test, a one percent change in the slope of the ramp would change the expected number of, codes by one percent. Since these errors would quickly accumulate, the integral nonlinearity test would become unfeasible. From brief consideration it is clear that the input source should have better precision than the converter being tested. When a sine wave is used, an error is produced, which becomes larger near the peaks. However, this error can be made as small and desired by sufficiently overdriving the A/D converter.
The probability density p(V) for a function of the form A sin ωt is
Integrating this density with respect to voltage gives the distribution function P(V a , V b )
which is in essence, the probability of a sample being in the range V a to V b . If the input has a dc offset, it has the form V o + A sin ωt with density
The new distribution is shifted by V o as expected
The statistically correct method to measure the nonlinearities is to estimate the transitions from the data. The ratio of bin width to the ideal bin width P(i) is the differential linearity and should be unity.
Subtracting on LSB gives the differential nonlinearity in LSBs
Replacing the function P(V a , V b ) by the measured frequency of occurrence H/N t , taking the cosine of both sides of (A.67) and solving for \( {\hat{V}_b} \), which is an estimate of V b , and using the following identities
yields to
In this consideration, the offset V o is eliminated, since it does not effect the integral or differential nonlinearity. Solving for \( {\hat{V}_b} \)and using the positive square root term as a solution so that \( {\hat{V}_b} \) is greater than V a
This gives \( {\hat{V}_b} \)in terms of V a . \( {\hat{V}_k} \) can be computed directly by using the boundary condition V o = −A and using
the estimate of the transition level \( {\hat{V}_b} \)denoted as a T k can be expressed as
A is not known, but being a linear factor, all transitions can be normalized to A so that the full range of transitions is ±1.
6.1.7 B.2 Mean Square Error
As the probability density function associated with the input stimulus is known, the estimators of the actual transition level T k and of the corresponding INL k value expressed in least significant bits (LSBs) are represented as random variables defined, respectively, for a coherently sampled sinewave
where A, d, θ 0 are the signal amplitude, offset and initial phase, respectively, M is the number of collected data, D/M represents the ratio of the sinewave over the sampling frequencies. T k i is the ideal kth transition voltage, and Δ = FSR/2B is the ideal code-bin width of the ADC under test, which has a full-scale range equal to FSR. A common model employed for the analysis of an analog-to digital converter affected by integral nonlinearities describes the quantization error ε as the sum of the quantization error of a uniform quantizer ε q and the nonlinear behavior of the considered converter ε n . For simplicity assuming that |INL k | < Δ/2, we have:
where sgn(.) and i(.) represent the sign and the indicator functions, respectively, s denotes converter stimulus signal and the non-overlapping intervals I k are defined as
The nonlinear quantizer mean-square-error, evaluated under the assumption of uniform stimulation of all converter output codes, is given by
where f s represent PDF of converter stimulus. Stimulating all device output codes with equal probability requires that
Thus, mse becomes
Assuming Δ = (V M -V m )/N, and exploiting the fact the mse associated with the uniform quantization error sequence is Δ 2 /12
Since, for a rounding quantizer, ε q (s) = Δ/2−Δ(s/Δ−1/2), it can be verified that sgn(INL k ) · ε q (s) < 0, so that
When characterizing A/D converters the SINAD is more frequently used than the mse. The SINAD is defined as
Let the amplitude of the input signal be A dBFS , expressed in dB relative full scale. Hence, the rms value is then
The rms (noise) amplitude is obtained from the mse expression above so that
To calculate the effective number of bits ENOB, firstly express the SINAD for an ideal uniform ADC and than solve for b
Letting the amplitude A = 10A(dBFS)/20 FSR/2, and incorporating above equation, the ENOB can be expressed as
6.1.8 B.3 Measurement Uncertainty
To estimate the uncertainty on the DNL and INL it is necessary to know the probability distribution of the cumulative probability Q i to realize a measurement V < UB i , with UB i the uperbound of the ith level
and using linear transformation
The variance and cross-correlation of UB i is derived using linear approximations. To realize the value Q i , it is necessary to have N i measurements with a value <UB i , and (N − N i ) measurements with a value >UB i . The distribution of Q i is a binomial distribution, which can be very well approximated by a normal distribution [414]
with Q i ’ the estimated value of Q i . The mean and the standard deviation is given by
which states that Q i ’ is an unbiased estimate of Q i . To calculate the covariance between Q i and Q j , firstly, let’s define
and the relation
which leads to
with
or
To calculate the variance σ UB 2
Similarly,
Since the differential nonlinearity of the ith level is defined as the ratio
where L R is the length of the record, the uncertainty in DNL i and INL i measurements can be expressed as
The maximal uncertainty occurs for Q i = 0.5, thus the previous equation can be approximated with
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Zjajo, A., de Gyvez, J.P. (2011). Conclusions and Recommendations. In: Low-Power High-Resolution Analog to Digital Converters. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9725-5_6
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