Abstract
Chapter 2 describes the Track and Hold (T&H) architecture for a time-interleaved ADC. Mismatch between channels, like difference in offset, gain and timing, degrades the performance and therefore this topic is investigated in detail.
Two T&H architectures are discussed, one with a frontend sampler and one without. The use of a frontend sampler has the advantage of good timing alignment between channels, the resistance of the switch is however a problem: it limits both the input bandwidth and the achievable resolution and the track-time has to be less than one sample period.
A new open-loop buffer is introduced together with a new technique to increase its bandwidth. The result of this combination is a T&H buffer with good linearity and high bandwidth, while the power consumption is kept low.
The topic of calibration is discussed and while offset and gain calibrations are relatively easy to implement, timing calibration is much harder to realize: it requires high-frequency test-signals and the required adjustable timing circuitry causes jitter by itself.
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Notes
- 1.
In this example, only 2 samples per period are of importance, so the square-wave can also be replaced by a sine-wave.
- 2.
The relation between the scales in dB and bits is: dB≈6.02n+1.76.
- 3.
The amount of channel charge dump mainly depends on the area of the transistor channel. Since sample switches usually have a large aspect ratio (large W, small L) e.g. 10/0.13, a small absolute variation in W has little impact, while the same absolute variation in L has a much larger impact. The relative mismatch in charge dump is therefore quite independent on W, resulting in an absolute mismatch proportional to W. So, increasing the switch width leads to an increase in the mismatch of the charge dump. For a bootstrapped sample-switch this results in increased offset mismatch. As offset calibration is often required for time-interleaved ADCs, this is not considered to be a problem.
- 4.
A derivation is given in Sect. 3.2.2 starting at p. 42. However, a step-size of half the range is assumed there, while here the step-size equals the entire range for an input signal at the Nyquist frequency. Therefore, n needs to be replaced by n+1.
- 5.
This buffer does use feedback, but it is only local.
- 6.
Increasing the number of phase shifted input signals does not only remove harmonics. For example, when going from 2 to 3 signals, some even-order harmonics appear again.
- 7.
- 8.
This is in contrast with the buffers after the T&H switch, as these have relaxed speed requirements due to the interleaving [26].
- 9.
Depending on the architecture, the capacitance increases between 4 and 8 times more per bit.
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Louwsma, S., van Tuijl, E., Nauta, B. (2011). Time-interleaved Track and Holds. In: Time-interleaved Analog-to-Digital Converters. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9716-3_2
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