Abstract
The proposed time-interleaved ADC [1] has been fabricated in a 0.18 μm one-poly six-metal CMOS process. The chip samples are packaged in 68-pin Ceramic Quad Flat-Pack (CQFP) packages. The successful measurement of a several-hundred MHz ADC is not a trivial task, and a special attention is necessary in the Printed-Circuit Board (PCB) design as well as the measurement setup that must ensure signal integrity. This chapter will present the design of the PCB with the consideration of high-frequency performance, and the testing setup in order to validate the design. The measurement results of the ADC will be exposed and a comparison with state-of-the-art low-voltage ADCs is presented.
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Sin, SW., U, SP., Martins, R.P. (2010). Experimental Results. In: Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9710-1_6
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