Testing Logic Circuits for Probabilistic Faults

Abstract

Testing circuit vulnerability to probabilistic faults, like single-event upsets (SEUs), requires a reformulation of test-generation methods. Unlike in traditional testing, a probabilistic fault can be detected by different test vectors with different probabilities, i.e., they have different sensitivities to probabilistic faults. We develop an efficient PTM-based algorithm to compute test-vector sensitivity. We also propose several test generation and compaction methods for probabilistic faults, with the goals of estimating and bounding fault detection probabilities. These methods use integer linear programming (ILP) to optimize test sets. The results show that our methods can generate tests quickly and require only half as many (repeated) vectors as testing with random patterns.