Abstract
We propose a general mathematical tool, the probabilistic transfer matrix (PTM), to reason about logic circuit behavior. PTMs provide a concise description of both normal and faulty behavior and are well-suited to reliability analysis. Simple composition rules based on connectivity can be used to recursively build large, circuit PTMs from smaller gate PTMs. Circuit PTMs can be used to accurately calculate joint output probabilities in the presence of reconvergent fan-out and inseparable joint input distributions using a small set of matrix operations, some of which we define. We demonstrate the use of PTMs in capturing various sorts of errors inherent in nanocircuits. We also show the use of PTMs in deriving polynomial approximations for circuit error probabilities in terms of gate error probabilities for the purpose of determining thresholds of acceptable gate error for specific circuits.
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Notes
- 1.
The \(eliminate\_variables\) operation is analogs to the existential abstraction of a set of variables \(x\) in a Boolean function \(f\) [8], given by the sum of the positive and negative cofactors of \(f\), with respect to \(x\): \(\exists x \ f=f_x+f_{\overline{x}}\). The \(eliminate\_variables\) operation for PTMs relies on arithmetic addition of matrix entries instead of the Boolean disjunction of cofactors.
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Krishnaswamy, S., Markov, I.L., Hayes, J.P. (2013). Probabilistic Transfer Matrices. In: Design, Analysis and Test of Logic Circuits Under Uncertainty. Lecture Notes in Electrical Engineering, vol 115. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9644-9_2
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DOI: https://doi.org/10.1007/978-90-481-9644-9_2
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