Skip to main content
SpringerLink
Log in

Timing Closure

  • Chapter
  • First Online:
VLSI Physical Design: From Graph Partitioning to Timing Closure

Abstract

The layout of an integrated circuit (IC) must not only satisfy geometric requirements, e.g., non-overlapping cells and routability, but also meet the design’s timing constraints, e.g., setup (long-path) and hold (short-path) constraints. The optimization process that meets these requirements and constraints is often called timing closure. It integrates point optimizations discussed in previous chapters, such as placement (Chap. 4) and routing (Chaps. 5–7), with specialized methods to improve circuit performance.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 69.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 89.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Chapter 8 References

  1. C. J. Alpert, M. Hrkic, J. Hu and S. T. Quay, “Fast and Flexible Buffer Trees that Navigate the Physical Layout Environment”, Proc. Design Autom. Conf., 2004, pp. 24–29.

    Google Scholar 

  2. C. J. Alpert, J. Hu, S. S. Sapatnekar and C. N. Sze, “Accurate Estimation of Global Buffer Delay Within a Floorplan”, IEEE Trans. on CAD 25(6) (2006), pp. 1140–1146.

    Google Scholar 

  3. C. J. Alpert, T. C. Hu, J. H. Huang and A. B. Kahng, “A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-Driven Global Routing”, Proc. Intl. Conf. on Circuits and Sys., 1993, pp. 1869–1872.

    Google Scholar 

  4. C. J. Alpert, S. K. Karandikar, Z. Li, G.-J. Nam, S. T. Quay, H. Ren, C. N. Sze, P. G. Villarrubia and M. C. Yildiz, “Techniques for Fast Physical Synthesis”, Proc. IEEE 95(3) (2007), pp. 573–599.

    Google Scholar 

  5. C. J. Alpert, D. P. Mehta and S. S. Sapatnekar, eds., Handbook of Algorithms for Physical Design Automation, CRC Press, 2009.

    Google Scholar 

  6. K. D. Boese, A. B. Kahng and G. Robins, “High-Performance Routing Trees with Identified Critical Sinks”, Proc. Design Autom. Conf., 1993, pp. 182–187.

    Google Scholar 

  7. M. Burstein and M. N. Youssef, “Timing Influenced Layout Design”, Proc. Design Autom. Conf., 1985, pp. 124–130.

    Google Scholar 

  8. T. F. Chan, J. Cong and E. Radke, “A Rigorous Framework for Convergent Net Weighting Schemes in Timing-Driven Placement”, Proc. Intl Conf. on CAD, 2009, pp. 288–294.

    Google Scholar 

  9. K.-H. Chang, I. L. Markov and V. Bertacco, “Postplacement Rewiring by Exhaustive Search for Functional Symmetries”, ACM Trans. on Design Autom. of Electronic Sys. 12(3) (2007), pp. 1–21.

    Google Scholar 

  10. A. Chowdhary, K. Rajagopal, S. Venkatesan, T. Cao, V. Tiourin, Y. Parasuram and B. Halpin, “How Accurately Can We Model Timing in a Placement Engine?”, Proc. Design Autom. Conf., 2005, pp. 801–806.

    Google Scholar 

  11. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, “Provably Good Algorithms for Performance-Driven Global Routing”, Proc. Intl. Symp. on Circuits and Sys., 1992, pp. 2240–2243.

    Google Scholar 

  12. A. E. Dunlop, V. D. Agrawal, D. N. Deutsch, M. F. Jukl, P. Kozak and M. Wiesel, “Chip Layout Optimization Using Critical Path Weighting”, Proc. Design Autom. Conf., 1984, pp. 133–136.

    Google Scholar 

  13. W. C. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers”, J. Applied Physics 19(1) (1948), pp. 55–63.

    Article  Google Scholar 

  14. H. Eisenmann and F. M. Johannes, “Generic Global Placement and Floorplanning”, Proc. Design Autom. Conf., 1998, pp. 269–274.

    Google Scholar 

  15. S. Ghiasi, E. Bozorgzadeh, P.-K. Huang, R. Jafari and M. Sarrafzadeh, “A Unified Theory of Timing Budget Management”, IEEE Trans. on CAD 25(11) (2006), pp. 2364–2375.

    Google Scholar 

  16. B. Halpin, C. Y. R. Chen and N. Sehgal, “Timing Driven Placement Using Physical Net Constraints”, Proc. Design Autom. Conf., 2001, pp. 780–783.

    Google Scholar 

  17. P. S. Hauge, R. Nair and E. J. Yoffa, “Circuit Placement for Predictable Performance”, Proc. Intl. Conf. on CAD, 1987, pp. 88–91.

    Google Scholar 

  18. T. I. Kirkpatrick and N. R. Clark, “PERT as an Aid to Logic Design”, IBM J. Research and Development 10(2) (1966), pp. 135–141.

    Article  MATH  Google Scholar 

  19. J. Lillis, C.-K. Cheng, T.-T. Y. Lin and C.-Y. Ho, “New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing”, Proc. Design Autom. Conf., 1996, pp. 395–400.

    Google Scholar 

  20. R. Nair, C. L. Berman, P. S. Hauge and E. J. Yoffa, “Generation of Performance Constraints for Layout”, IEEE Trans. on CAD 8(8) (1989), pp. 860–874.

    Google Scholar 

  21. M. Orshansky and K. Keutzer, “A General Probabilistic Framework for Worst Case Timing Analysis”, Proc. Design Autom. Conf., 2002, pp. 556–561.

    Google Scholar 

  22. M. Orshansky, S. Nassif and D. Boning, Design for Manufacturability and Statistical Design: A Constructive Approach, Springer, 2008.

    Google Scholar 

  23. R. H. J. M. Otten and R. K. Brayton, “Planning for Performance”, Proc. Design Autom. Conf., 1998, pp. 122–127.

    Google Scholar 

  24. D. A. Papa, T. Luo, M. D. Moffitt, C. N. Sze, Z. Li, G.-J. Nam, C. J. Alpert and I. L. Markov, “RUMBLE: An Incremental, Timing-Driven, Physical-Synthesis Optimization Algorithm”, IEEE Trans. on CAD 27(12) (2008), pp. 2156–2168.

    Google Scholar 

  25. S. M. Plaza, I. L. Markov and V. Bertacco, “Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring”, IEEE Trans. on CAD 27(12) (2008), pp. 2107–2119.

    Google Scholar 

  26. K. Rajagopal, T. Shaked, Y. Parasuram, T. Cao, A. Chowdhary and B. Halpin, “Timing Driven Force Directed Placement with Physical Net Constraints”, Proc. Intl. Symp. on Phys. Design, 2003, pp. 60–66.

    Google Scholar 

  27. H. Ren, D. Z. Pan and D. S. Kung, “Sensitivity Guided Net Weighting for Placement Driven Synthesis”, IEEE Trans. on CAD 24(5) (2005) pp. 711–721.

    Google Scholar 

  28. J. A. Roy, N. Viswanathan, G.-J. Nam, C. J. Alpert and I. L. Markov, “CRISP: Congestion Reduction by Iterated Spreading During Placement”, Proc. Intl. Conf. on CAD, 2009, pp. 357–362.

    Google Scholar 

  29. M. Sarrafzadeh, M. Wang and X. Yang, Modern Placement Techniques, Kluwer, 2003.

    Google Scholar 

  30. R. S. Shelar, “Routing With Constraints for Post-Grid Clock Distribution in Microprocessors”, IEEE Trans. on CAD 29(2) (2010), pp. 245–249.

    Google Scholar 

  31. R. S. Shelar and M. Patyra, “Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor”, Proc. Intl. Symp. on Phys. Design, 2010, pp. 145–152.

    Google Scholar 

  32. I. Sutherland, R. F. Sproull and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann, 1999.

    Google Scholar 

  33. H. Tennakoon and C. Sechen, “Nonconvex Gate Delay Modeling and Delay Optimization”, IEEE Trans. on CAD 27(9) (2008), pp. 1583–1594.

    Google Scholar 

  34. M. Vujkovic, D. Wadkins, B. Swartz and C. Sechen, “Efficient Timing Closure Without Timing Driven Placement and Routing”, Proc. Design Autom. Conf., 2004, pp. 268–273.

    Google Scholar 

  35. J. Westra and P. Groeneveld, “Is Probabilistic Congestion Estimation Worthwhile?”, Proc. Sys. Level Interconnect Prediction, 2005, pp. 99–106.

    Google Scholar 

  36. Y. Xie, J. Cong and S. Sapatnekar, eds., Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures, Springer, 2010.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Departments of CSE and ECE, University of California at San Diego, #0404, 92093, La Jolla, California, USA

    Andrew B. Kahng

  2. Electrical Engineering and Information Technology, Dresden University of Technology, Helmholtzstr. 10, 01069, Dresden, Germany

    Jens Lienig

  3. Electrical Engineering and Computer Science, University of Michigan, 2260 Hayward St., 48109, Ann Arbor, Michigan, USA

    Igor L. Markov & Jin Hu

Authors
  1. Andrew B. Kahng
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jens Lienig
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Igor L. Markov
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Jin Hu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Andrew B. Kahng .

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media B.V.

About this chapter

Cite this chapter

Kahng, A.B., Lienig, J., Markov, I.L., Hu, J. (2011). Timing Closure. In: VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9591-6_8

Download citation

  • DOI: https://doi.org/10.1007/978-90-481-9591-6_8

  • Published:

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-9590-9

  • Online ISBN: 978-90-481-9591-6

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation