Abstract
The primary task of synthesis approaches is to generate circuits that realize the desired functions. Secondarily, it should be ensured that the resulting circuits are as compact as possible. However, the results obtained by synthesis approaches often are sub-optimal. Consequently, in common design flows optimization approaches are applied after synthesis. In this chapter, three new optimization approaches are introduced—each with an own focus on a particular cost metric. The first one considers the reduction of the well-established quantum cost (used in quantum circuits) and the transistor cost (used in CMOS implementations), respectively. The second approach considers the line count in a circuit. Finally, an optimization method is introduced which takes so called Nearest Neighbor Cost (NNC) into account.
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Notes
- 1.
This took over 10 hours of computation time. Furthermore, the application to the urf series of circuits (which are quite large) has been aborted because they required too much run-time.
- 2.
Of course, similar results are also achieved if the proposed approach is directly applied to non-optimized circuits.
- 3.
In other words, the cone of influence of the garbage output line l g is considered.
- 4.
Including both, the number of primary inputs/outputs as well as the number of additional circuit lines.
- 5.
Note that thereby still the number of primary inputs/outputs are considered which cannot be reduced.
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Wille, R., Drechsler, R. (2010). Optimization. In: Towards a Design Flow for Reversible Logic. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9579-4_6
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