Strength Reduction of Multipliers

Abstract

This chapter presents a conversion technique for constant multiplications. The targeted multiplication operations (or MULs), which form a significant part of all MULs, are converted into (a number of) less complex, cheaper operations. Multiplier strength reduction is a well-known technique in hardware synthesis and has been used extensively for filter design in custom hardware. However, the specific context of embedded processors presents opportunities and trade-offs that have not been exploited before. The presented strength reduction significantly extends current multiplier strength reduction in compilers and can depend on a cost function in order to optimize performance, area, energy consumption and even operator accuracy, according to the requirements of a specific context. This approach enables the conversion of many more multiplications than are currently converted by state-of-the-art techniques. One of the main ways to exploit this transformation has been described in Chapter 9 where the SoftSIMD concept strongly benefits from the conversion of hardware multiplications into shift-and-add operations.