Abstract
In this chapter, we introduce the details of how the transmitter jitter can be decomposed in a way that is fast and accurate enough to be implemented in a production environment. The jitter can be extracted from either the time domain or the frequency domain. We also propose a hybrid approach to improve accuracy while keep test time short. The advantages and disadvantages of each of the proposed method are discussed, such that the best method can be selected for task at hand. Finally, a set of experiments is undertaken to validate the proposed approaches.
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Reference
Y. Fan, Y. Cai and Z. Zilic, "A High Accuracy, High Throughput Jitter Test Solution on ATE for 3 Gbps and 6 Gbps Serial-ATA," Proceedings of IEEE International Test Conference, Oct. 2007
S. Sunter, A. Roy, and J. Cote, “An Automated, Complete, Structural Test Solution for SERDES,” Proceedings of IEEE International Test Conference, 2004
W. Fritzsche and A. Haque, “Low Cost Testing of Multi-GBit Device Pins with ATE Assisted Loopback Instrument,” Proceedings of IEEE International Test Conference, Oct. 2008
A. Meixner, A. Kakizawa, B. Provost, and S. Bedwani, “External Loopback Testing Experience with High Speed Serial Interfaces,” Proceedings of IEEE International Test Conference, Oct. 2008
B. Laquai and Y. Cai “Testing Multilane Gigabit SerDes Interfaces with Jitter Injection,” Proceedings of IEEE International Test Conference, 2001
M. Li, J.Wilstrup, R. Ressen and D. Petrich, “A New Method for Jitter Decomposition through Its Distribution Tail Fitting,” Proceedings of IEEE International Test Conference, 1999
Tektronix, "Jitter Measurement and Timing Analysis," Product guideline, http://www.tek.com/applications/serial_data/jitter.html
“Standard Error of the Mean,” material from Brighton Webs Ltd, statistical and data services for industry. http://www.brighton-webs.co.uk/statistics/standard_error.asp
Analyzing Jitter Using a Spectrum Approach, Tektronix Application note
G. Hansel, K. Stieglbauer, K. Schulze and J. Moreira, “Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE”, Proceedings of IEEE International Test Conference, 2004
Agilent Technologies, "Jitter Solutions for Telecom, Enterprise, and Digital Designs," Cooperate literature, http://cp.literature.agilent.com/litweb/pdf/5988-9592EN.pdf
Standard Error (Statistics) http://en.wikipedia.org/wiki/Standard_error_(statistics)
Teradyne, Inc. http://www.teradyne.com
B.A. Ward,K. Tan, and M.L. Guenther, "Apparatus and Method for Spectrum Analysis-Based Serial Data Jitter Measurement," US Patent No. 6832172, issued on December 14, 2004
M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, Oxford University Press, 2001
Y. Cai, S. Werner, G. Zhang, M. Olsen, and R. Brink, “Jitter Testing for Multi-gigabit Backplane SerDes – Techniques to Decompose and Combine Various Types of Jitter,” Proceedings of IEEE International Test Conference, 2002, p700-709
D. C. Keezer, D. Minier and P. Ducharme, “Method for Reducing Jitter in Multi-Gigahertz ATE,” Proceedings of the Conference on Design, Automation and Test in Europe, 2007, Pages 701-706
A. H. Chan and G. W. Roberts, “A Jitter Characterization System Using a Component-Invariant Vernier Delay Line,” IEEE Transactions on VLSI Systems, Volume 12, Issue 1, Jan. 2004
Y. Cai, A. Bhattacharyya, J. Martone, A. Verma, and W. Burchanowski, “A Comprehensive Production Test Solution for 1.5 GB/S and 3 GB/S Serial-ATA,” Proceedings of IEEE International Test Conference, 2005
W. Dalal and D. Rosenthal, “Measuring Jitter of High Speed Data Channels Using Undersampling Techniques,” Proceedings of IEEE International Test Conference, 1998
Serial ATA International Organization: Serial ATA Revision 3.0. Gold Revision, June 2, 2009
M. Hafed, D. Watkins, C. Tam, and B. Pishdad, “Massively Parallel Validation of High-speed Serial Interfaces Using Compact Instrument Modules,” Proceedings of IEEE International Test Conference, 2006
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Fan, Y., Zilic, Z. (2011). Transmitter Jitter Extractions on ATE. In: Accelerating Test, Validation and Debug of High Speed Serial Interfaces. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9398-1_4
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DOI: https://doi.org/10.1007/978-90-481-9398-1_4
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