On-Chip Circuit Technique for Measuring Jitter and Skew with Picosecond Resolution

Abstract

When VLSI circuits operate at multi-GHz frequencies, the demand for precise clock generation and distribution become more and more stringent. Inevitably, clock edges develop timing jitter, which is the deviation of the timing of the clock edges from their ideal values. Jitter arises from power supply noise on the circuits which distribute the clock, and from the phase-locked loops (PLLs) which generate a high frequency clock by multiplying a very stable lower frequency signal. Since computation requires that certain logical operations are completed within each clock cycle, a certain amount of jitter is assumed in the design of a chip, by including it in the clock budget. Jitter which is too large can impact the allowed clock budget, or even cause data transmission and computation errors. The measurement of jitter is required for high-speed circuits, to determine if timing specifications and margins are met. In contemporary circuits, where clock periods may be as small as 250 or 300 ps, rms jitter may be required to be as small as a few picoseconds. Conventional measurement of such small timing delays requires driving the signal of interest off-chip with high fidelity off chip drivers. Measurement is performed with a high performance oscilloscope or similar instrument, limiting characterization to only a few samples.