Abstract
With various powerful features integrated in mobile devices, the demand for high-density, low-power, and low-leakage design keeps elevating. In 65 nm technologies and below, process intra-die variability becomes a prominent design factor.Two types of intra-die variability exist: one is spatially correlated and the other is random. In this chapter, we focus on intra-die random variability, shorted as the variability and its impact on circuit timing failure. The variability is independent in nature. It can have a large impact on circuit performance and robustness. This is especially true for nanometer low-power (LP) CMOS designs, where the over-drive voltage is less than two times of the threshold voltage. As the voltage scales down, circuits become increasingly sensitive to the variability. As a result, circuit design for low-power process technologies with low supply voltages becomes extremely challenging.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
C. Visweswariah, Death, taxes and failing chips, in Proceedings of Design Automation Conference, June 2003, pp. 343–347
F.N. Najm, N. Menezes, Statistical timing analysis based on a timing yield model, in Proceedings of the Design Automation Conference, June 2004, pp. 460–465
D. Agarwal, V. Blaauw, S. Zolotov, S. Vruduhula, Computation and refinement of statistical bounds on circuit delay, in Proceedings of the Design Automation Conference, June 2003, pp. 348–353
P.S. Zuchowski, P.A. Habitz, J.D. Hayes, J.H. Oppold, Process and environmental variability impacts on ASIC timing, in Proceedings of the International Conference on Computer-Aided Design, Nov 2004, pp. 336–342
S. Borker, et. al., Parameter variability and impact on circuits and microarchitecture, in Proceedings of the IEEE/ACM International Design Automation Conference, June 2003, pp. 338–342
T.C. Chen, Where CMOS is going: trendy vs. real technology, IEEE Solid State Circuits Society Newsletter, 20(3), Sept 2006
Y. Huang et al. Efficient diagnosis for multiple intermittent scan chain hole-time faults, in Proceedings of the 12th Asian Test Symposium (ATS’03), 2003
Amitava Majumdar et. al., Hold-time validation on silicon and the relevance of hazards in timing analysis, in Proceedings of the Design Automation Conference, 2006, pp. 326–339
Enrico Malavasi, et al. Impact analysis of process variability on clock skew, in Proceedings of the International Symposium on Quality Electronic Design, 2002
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer Science+Business Media B.V.
About this chapter
Cite this chapter
Zhang, X., Bai, X. (2010). Process Variability-Induced Timing Failures – A Challenge in Nanometer CMOS Low-Power Design. In: Amara, A., Ea, T., Belleville, M. (eds) Emerging Technologies and Circuits. Lecture Notes in Electrical Engineering, vol 66. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9379-0_12
Download citation
DOI: https://doi.org/10.1007/978-90-481-9379-0_12
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-90-481-9378-3
Online ISBN: 978-90-481-9379-0
eBook Packages: EngineeringEngineering (R0)