Abstract
The process of embedded system design on reconfigurable architectures needs smart solutions to reduce development life-cycle and to use resources efficiently at run-time. Current solutions are insufficient to enable the embedded system designer to reflect the flexibility that a reconfigurable architecture can offer. Some of the basic problems are lack of flexible operator definitions, very detailed hardware abstraction procedures, a few or no constraints for tasks or loops at the high-level of design abstraction. In this work, we propose a new model for automated design of application-specific processors in run-time reconfigurable architectures, solving the aforementioned inefficiency problems. Based on the proposal, a design language, a framework and a compiler have also been developed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Altera Corporation, Nios embedded processor, 2007.
J.A. Bower, et al., A java-based system for fpga programming. FPGA World Conference, 2008.
W.O. Cesario, et al., Colif: a design representation for application-specific multiprocessor socs. IEEE Des. Test 18, 8–20, 2001.
F.P. Coyle, M.A. Thornton, From UML to HDL: a model driven architectural approach to hardware-software co-design. Information Systems: New Generations Conference (ISNG), vol. 1., 88–93, 2005.
R. Damasevicius, A subset-based comparison of main design languages. Inf. Tech. Cont. Technol. 1, 49–56, 2004.
A. Fauth, J, Praet, M. Freericks, Describing instruction set processors using nML. EDTC’95, pp. 503–507, 1995.
Freescale Semiconductor Inc., CodeWarrior development tools, 2007.
R.E. Gonzalez, Xtensa: a configurable and extensible processor. IEEE Micro 20, 60–70, 2000.
A. Halambi, et al., A customizable compiler framework for embedded systems. SCOPES, 2001.
T. Kambe, A. Yamada, M. Yamaguchi, Trend of system level design and an approach to c-based design. Microelec. J. 33, 875–880, 2002.
B. Kurumahmut, RH(+): the model for high-level embedded system design on run-time reconfigurable hardware. Master’s thesis, Bogazici University, Computer Engineering, 2007.
B. Mei, et al., Architecture exploration for a reconfigurable architecture template. IEEE Des. Test 22, 90–101, 2005.
S.J. Mellor, Executable and translatable UML, 2003.
S.V. Nikolaos, M. Konstantinos, System Level Design of Reconfigurable Systems-on-Chip. Springer, Dordrecht, The Netherlands, 2005.
Open SystemC Initiative, www.systemc.org., 2009.
R.A. Orchard, Fuzzyclips version 6.04a Users’ guide, 1998.
I.R. Quadri, S. Meftali, J.L. Dekeyser, High level modeling of dynamic reconfigurable fpgas. International Journal of Reconfigurable Computing, vol. 2009, Article ID 408605, 2009. doi:10.1155/2009/408605.
C. Raistrick, P. Francis, J. Wright, Model Driven Architecture with Executable UML(TM). New York, NY, Cambridge University Press, 2004.
O. Schliebusch, et al., Architecture implementation using the machine description language lisa. ASP-DAC’02, pp. 239–244, 2002.
Silicon Hive, HiveCC software development kit v3.5., 2009.
SpecC Technology Open Consortium, SpecC language reference manual, version 2.0., 2002.
Synfora Inc., www.synfora.com., 2009.
Target Compiler Tech., CHESS/CHECKERS: a retargetable tool-suite for embedded processors. Technical report, Belgium, 2003.
S. Vassiliadis, et al., The MOLEN polymorphic processor. IEEE Trans. Comp. 53, 1363–1375 (2004).
Xilinx Inc., www.xilinx.com., 2007.
P. Yiannacouras, J. Rose, J.G. Steffan, The microarchitecture of fpga-based soft processors. CASES’05, pp. 202–212, 2005.
V. Zivojnovic, S. Pees, H. Meyr, LISA-machine description language and generic machine model for HW/SW co-design. IEEE Workshop on VLSI Signal Processing IX, pp. 127–136, 1996.
Acknowledgements
This work has been partially supported by the Turkish Foundation of Science and Technology, under Kariyer Research Project Program (pr.no:104E038). We also would like to thank to anonymous reviewers who have helped us to improve the quality of this article.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer Science+Business Media B.V.
About this chapter
Cite this chapter
Yurdakul, A., Ghamari, R., Kurumahmut, B., Kabukcu, G. (2010). Design Automation Model for Application-Specific Processors on Reconfigurable Fabric. In: Borrione, D. (eds) Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s. Lecture Notes in Electrical Engineering, vol 63. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9304-2_7
Download citation
DOI: https://doi.org/10.1007/978-90-481-9304-2_7
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-90-481-9303-5
Online ISBN: 978-90-481-9304-2
eBook Packages: EngineeringEngineering (R0)