Abstract
A power scalable ADC for use in sub-sampled systems is described. Low power is achieved using a technique to eliminate the front-end sample and hold. Measured results of a prototype in a 1.8V, 0.18μm CMOS process show a power of only 27mW for a 10-bit pipelined ADC at 50MS/s - a greater than 20% reduction in power versus a similar design which requires a front-end sample and hold.
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Ahmed, I. (2010). A Sub-sampling ADC with Embedded Sample-and-Hold. In: Pipelined ADC Design and Enhancement Techniques. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-8652-5_8
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DOI: https://doi.org/10.1007/978-90-481-8652-5_8
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