Abstract
A 11-bit 45MS/s pipelined ADC with rapid background calibration of both DAC and gain errors is described. A dual ADC technique is used to achieve calibration within only 104 clock cycles - several orders of magnitude faster than prior state of the art. Measured results from a prototype in a 1.8V, 0.18μm CMOS process show calibration to improve the peak INL of the ADC from 6.4 LSB to 1.1 LSB.
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References
Ahmed, I., Johns, D.A.: An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage. Solid-State Circuits Conference, 2007. ESSCIRC 2007. Proceedings of the 33rd European, pp. 147–150, 11–13 Sept 2007
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Ahmed, I. (2010). Rapid Calibration of DAC and Gain Errors in a Multi-bit Pipeline Stage. In: Pipelined ADC Design and Enhancement Techniques. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-8652-5_6
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DOI: https://doi.org/10.1007/978-90-481-8652-5_6
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