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ADC Architectures

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Pipelined ADC Design and Enhancement Techniques

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

Abstract

An overview of ADCs and key performance requirements in ADCs is given. An introduction to popular Nyquist rate ADC architectures such as SAR and Flash are given. Sub-sampling is shown as a technique to eliminate a mixer before an ADC.

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References

  1. Johns, D., Martin, K.: Analog Integrated Circuit Design. Wiley, New York (1997)

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  4. Craninckx, J., Van der Plas, G.: A 65fJ/Conversion-step 0-to-50MS/s 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS. Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 246–600, 11–15 Feb 2007

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  5. Agnes, A., Bonizzoni, E., Malcovati, P., Maloberti, F.: A 9.4-ENOB 1V 3.8µW 100kS/s SAR ADC with time-domain comparator. Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, pp. 246–610, 3–7 Feb 2008

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Correspondence to Imran Ahmed .

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© 2010 Springer Science+Business Media B.V.

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Ahmed, I. (2010). ADC Architectures. In: Pipelined ADC Design and Enhancement Techniques. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-8652-5_2

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  • DOI: https://doi.org/10.1007/978-90-481-8652-5_2

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  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-8651-8

  • Online ISBN: 978-90-481-8652-5

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