Skip to main content
SpringerLink
Log in
Book cover

Compact Modeling pp 3–40Cite as

Surface-Potential-Based Compact Model of Bulk MOSFET

  • Chapter

Abstract

We review surface-potential-based approach to compact modeling of bulk MOS transistors and provide introduction to the widely used PSP model jointly developed by the Arizona State University and NXP Semiconductors. The emphasis is on the interplay between the mathematical structure of the compact model and its capabilities for the circuit design applications.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   119.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   159.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   199.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. Aarts, A.C.T., van der Hout, R., Paasschens, J.C.J., Scholten, A.J., Willemsen, M.B., Klaassen, D.B.M.: New fundamental insights into capacitance modeling of laterally nonuniform MOS devices. IEEE Trans. Electron Devices 53(2), 270–278 (2006)

    Article  Google Scholar 

  2. Arora, N.D., Gildenblat, G.S.: A semi-empirical model of the MOSFET inversion layer mobility for low-temperature operation. IEEE Trans. Electron Devices 34, 89–93 (1987)

    Article  Google Scholar 

  3. Bendix, P., Rakers, P., Wagh, P., Lemaitre, L., Grabinski, W., McAndrew, C.C., Gu, X., Gildenblat, G.: RF distortion analysis with compact MOSFET models. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 9–12, 3–6 October 2004

    Google Scholar 

  4. Boothroyd, A.R., Tarasewicz, S.W., Slaby, C.: MISNAN—a physically based continuous MOSFET model for CAD applications. IEEE Trans. Electron Devices 10, 1512–1529 (1991)

    Google Scholar 

  5. Brews, J.R.: A charge-sheet model of the MOSFET. Solid-State Electron. 21, 345–355 (1978)

    Article  Google Scholar 

  6. Brews, J.R.: Threshold shifts due to nonuniform doping profiles in surface channel MOSFETs. IEEE Trans. Electron Devices ED-26, 1696 (1979)

    Article  Google Scholar 

  7. Choi, C.-H., Nam, K.-Y., Yu, Z., Dutton, R.W.: Impact of gate direct tunneling current on circuit performance: A simulation study. IEEE Trans. Electron Devices 48, 2823–2829 (2001)

    Article  Google Scholar 

  8. Cai, J., Sah, C.T.: Gate tunneling currents in ultrathin oxide metal–oxide–silicon transistors. J. Appl. Phys. 89(4), 2272–2285 (2001)

    Article  Google Scholar 

  9. Cao, K.M., Lee, W.C., Liu, W., Jin, X., Su, P., Fung, S.K.H., An, J.X., Yu, B., Hu, C.: BSIM4 gate leakage model including source-drain partition. In: IEDM Tech. Dig., pp. 815–818 (2000)

    Google Scholar 

  10. Chen, T.L., Gildenblat, G.: Analytical approximation for the MOSFET surface potential. Solid-State Electron. 45(2), 335–339 (2001)

    Article  Google Scholar 

  11. Chen, T.L., Gildenblat, G.: Symmetric bulk charge linearization of charge-sheet MOSFET model. Electron. Lett. 37(12), 791–793 (2001)

    Article  Google Scholar 

  12. Chen, J., Chan, T.Y., Ko, P.K., Hu, C.: Subbreakdown drain leakage current in MOSFET. IEEE Electron Device Lett. 8, 515–517 (1987)

    Article  Google Scholar 

  13. El-Mansy, Y.A., Boothroyd, A.R.: A simple two-dimensional model for IGFET operation in the saturation region. IEEE Trans. Electron Devices 24, 254–262 (1977)

    Article  Google Scholar 

  14. Enz, C.: An MOS transistor model for RF IC design valid in all regions of operation. IEEE Trans. Microw. Theory Tech. 50, 342–359 (2002)

    Article  Google Scholar 

  15. Ghibaudo, G., Roux-dit Buisson, O.: Low-frequency fluctuations in scaled down silicon CMOS devices status and trends. In: Proc. Eur. Solid-State Device Res. Conf., vol. 94, pp. 693–700 (1994)

    Google Scholar 

  16. Gildenblat, G., Chen, T.L.: Overview of an advanced surface-potential-based MOSFET model. In: Int. Conf. on Modeling and Simul. Microsyst., pp. 657–661 (2002)

    Google Scholar 

  17. Gildenblat, G., Chen, T.L., Bendix, P.: Analytical approximation for the perturbation of MOSFET surface potential by polysilicon depletion layer. Electron. Lett. 35, 1999 (1974)

    Google Scholar 

  18. Gildenblat, G., Cai, X., Chen, T.L., Gu, X., Wang, H.: Reemergence of the surface-potential-based compact models. In: IEDM Tech. Dig., pp. 863–866 (2003)

    Google Scholar 

  19. Gildenblat, G., Chen, T.L., Gu, X., Wang, H., Cai, X.: SP: an advanced surface-potential-based model. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 233–240 (2003)

    Google Scholar 

  20. Gildenblat, G., Wang, H., Chen, T.L., Cai, X.: SP: an advanced surface-potential-based compact MOSFET model. IEEE J. Solid-State Circuits 39, 1394–1406 (2004)

    Article  Google Scholar 

  21. Gildenblat, G., Li, X., Wu, W., Wang, H., Jha, A., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: PSP: an advanced surface-potential-based MOSFET model for circuit simulation. IEEE Trans. Electron Devices 53(9), 1979–1993 (2006)

    Article  Google Scholar 

  22. Gildenblat, G., Zhu, Z., McAndrew, C.C.: Surface potential equation for bulk MOSFET. Solid-State Electron. 53(1), 11–13 (2009)

    Article  Google Scholar 

  23. Grove, A.: Physics and Technology of Semiconductor Devices. Wiley, New York (1967)

    Google Scholar 

  24. Gu, X., Chen, T.L., Gildenblat, G., Workman, G.O., Veeraraghavan, S., Shapira, S., Stiles, K.: A surface potential-based compact model of n-MOSFET gate-tunneling current. IEEE Trans. Electron Devices 51(1), 127–135 (2004)

    Article  Google Scholar 

  25. Gu, X., Gildenblat, G., Workman, G., Veeraraghavan, S., Shapira, S., Stiles, K.: A surface-potential-based extrinsic compact MOSFET model. In: Tech. Proc. Nanotechnol. Conf., pp. 364–367 (2003)

    Google Scholar 

  26. Gu, X., Wang, H., Chen, T.L., Gildenblat, G.: Substrate current in surface-potential-based compact MOFET models. In: Tech. Proc. Nanotechnol. Conf., pp. 310–313 (2003)

    Google Scholar 

  27. Huang, C., Arora, N.: Characterization and modeling of the n- and p-channel MOSFET’s inversion-layer mobility in the range 25–125°C. Solid-State Electron. 37, 97–103 (1994)

    Article  Google Scholar 

  28. Hung, K.K., Ko, P.K., Hu, C., Cheng, Y.C.: A physics-based MOSFET noise model for circuit simulators. IEEE Trans. Electron Devices 37(5), 1323–1333 (1990)

    Article  Google Scholar 

  29. Hung, K.K., Ko, P.K., Hu, C., Cheng, Y.C.: A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors. IEEE Trans. Electron Devices 37(3), 654–665 (1990)

    Article  Google Scholar 

  30. Hwang, S., Yoon, T., Kwon, D., Yu, Y., Kim, K.: A physics-based, SPICE-compatible non-quasi-static MOS transient model based on the collocation method. Jpn. J. Appl. Phys. 37(2A), 119–121 (1998)

    Article  Google Scholar 

  31. Joardar, K., Gullapalli, K.K., McAndrew, C.C., Burnham, M.E., Wild, A.: An improved MOSFET model for circuit simulation. IEEE Trans. Electron Devices 45(1), 134–148 (1998)

    Article  Google Scholar 

  32. Kane, E.: Zener tunneling in semiconductors. J. Phys. Chem. Solids 12(2), 181–188 (1959)

    Article  MathSciNet  Google Scholar 

  33. Li, X., Wu, W., Jha, A., Gildenblat, G., Langevelde, R.V., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., McAndrew, C.C., Watts, J., Olsen, M., Coram, G., Chaudhry, S., Victory, J.: Benchmarking PSP compact model of MOS transistors. In: IEEE Int. Conf. on Microelectron. Test Structures, pp. 259–264 (2007)

    Google Scholar 

  34. Li, X., Wu, W., Jha, A., Gildenblat, G., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., McAndrew, C.C., Watts, J., Olsen, C.M., Coram, G.J., Chaudhry, S., Victory, J.: Benchmark tests for MOSFET compact models with application to the PSP model. IEEE Trans. Electron Devices 56(2), 243–251 (2009)

    Article  Google Scholar 

  35. Litwin, A.: Overlooked interfacial silicide-polysilicon gate resistance in MOS transistors. IEEE Trans. Electron Devices 48(9), 2179–2181 (2001)

    Article  Google Scholar 

  36. Liu, W., Bowen, C., Chang, M.C.: A CAD-compatible non-quasi-static MOSFET model. In: IEDM Tech. Dig., pp. 151–154 (1996)

    Google Scholar 

  37. Mancini, P., Turchetti, C., Masetti, G.: A non-quasi-static analysis of the transient behavior of the long-channel MOST valid in all regions of operation. IEEE Trans. Electron Devices ED-34, 325–334 (1987)

    Article  Google Scholar 

  38. McAndrew, C.C.: Practical modeling for circuit simulation. IEEE J. Solid-State Circuits 33(3), 439–448 (1998)

    Article  Google Scholar 

  39. McAndrew, C.C.: Validation of MOSFET model source-drain symmetry. IEEE Trans. Electron Devices 53(9), 2202–2206 (2006)

    Article  Google Scholar 

  40. McAndrew, C.C., Victory, J.J.: Accuracy of approximations in MOSFET charge models. IEEE Trans. Electron Devices 49(1), 72–81 (2002)

    Article  Google Scholar 

  41. Miura-Mattausch, M., Sadachika, N., Navarro, D., Suzuki, G., Takeda, Y., Miyake, M., Warabino, T., Mizukane, Y., Inagaki, R., Ezaki, T., Mattausch, H.J., Ohguro, T., Iizuka, T., Taguchi, M., Kumashiro, S., Miyamoto, S.: Hisim2: Advanced MOSFET model valid for RF circuit simulation. IEEE Trans. Electron Devices 53(9), 1994–2007 (2006)

    Article  Google Scholar 

  42. Mudanai, S., Shih, W.K., Rios, R., Xi, X., Rhew, J.H., Kuhn, K., Packan, P.: Analytical modeling of output conductance in long-channel halo-doped MOSFETs. IEEE Trans. Electron Devices 53(9), 2091–2097 (2006)

    Article  Google Scholar 

  43. Paasschens, J.C.J., Scholten, A.J., van Langevelde, R.: Generalizations of the Klaassen-Prins equation for calculating the noise of semiconductor device. IEEE Trans. Electron Devices 52(11), 2463–2472 (2005)

    Article  Google Scholar 

  44. Pao, H.C., Sah, C.T.: Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors. Solid-State Electron. 9, 927–937 (1966)

    Article  Google Scholar 

  45. Park, H.J., Ko, P.K., Hu, C.: A charge sheet capacitance model of short channel MOSFETs for SPICE. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 10(3), 376–389 (1991)

    Article  Google Scholar 

  46. PSP Group: PSP Manual Version 102.2 (2007). http://pspmodel.asu.edu/downloads/psp1022_summary.pdf

  47. Rios, R., Mudanai, S., Shih, W.K., Packan, P.: An efficient surface potential solution algorithm for compact MOSFET models. In: IEDM Tech. Dig., pp. 755–758 (2004)

    Google Scholar 

  48. Rios, R., Shih, W.K., Shah, A., Mudanai, S., Packan, P., Sandford, T., Mistry, K.: A three-transistor threshold voltage model for halo processes. In: IEDM Tech. Dig., pp. 113–116 (2002)

    Google Scholar 

  49. Sabnis, A.G., Clemens, J.T.: Characterization of the electron mobility in the inverted <100> Si surface. In: IEDM Tech. Dig., vol. 25, pp. 18–21 (1979)

    Google Scholar 

  50. Sah, C.T.: Fundamentals of Solid-State Electronics. World Scientific, Singapore (1991)

    Book  Google Scholar 

  51. Scharfetter, D.L., Gummel, H.K.: Large-signal analysis of a silicon read diode oscillator. IEEE Trans. Electron Devices 16, 64–77 (1969)

    Article  Google Scholar 

  52. Scholten, A.J., Tiemeijer, L.F., Vreede, P.W.H.D., Klaassen, D.B.M.: A large signal non-quasi-static MOS model for RF circuit simulation. In: IEDM Tech. Dig., pp. 5–8 (1999)

    Google Scholar 

  53. Scholten, A., Duffy, R., van Langevelde, R., Klaassen, D.: Compact modelling of pocket-implanted MOSFETs. In: Proc. Eur. Solid-State Device Res. Conf., pp. 311–314 (2001)

    Google Scholar 

  54. Scholten, A.J., Tiemeijer, L.F., van Langevelde, R., Havens, R.J., Zegers-van Duijnhoven, A.T.A., Venezia, V.C.: Noise modeling for RF CMOS circuit simulation. IEEE Trans. Electron Devices 50(3), 618–632 (2003)

    Article  Google Scholar 

  55. Scholten, A.J., Smit, G.D.J., Durand, M., van Langevelde, R., Klaassen, D.B.M.: The physical background of JUNCAP2. IEEE Trans. Electron Devices 53(9), 2098–2107 (2006)

    Article  Google Scholar 

  56. Scholten, A.J., van Langevelde, R., Tiemeijer, L.F., Klaassen, D.B.M.: Compact modeling of noise in CMOS. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 711–716 (2006)

    Google Scholar 

  57. Scholten, A.J., Smit, G.D.J., De Vries, B.A., Tiemeijer, L.F., Croon, J.A., Klaassen, D.B.M., van Langevelde, R., Li, X., Wu, W., Gildenblat, G.: The new CMC standard compact MOS model PSP: advantages for RF applications (invited). In: IEEE Radio Freq. Integr. Circuits Symp., pp. 247–250 (2008)

    Google Scholar 

  58. Scholten, A.J., Smit, G.D.J., De Vries, B.A., Tiemeijer, L.F., Croon, J.A., Klaassen, D.B.M., van Langevelde, R., Li, X., Wu, W., Gildenblat, G.: The new CMC standard compact MOS model PSP: advantages for RF applications. IEEE J. Solid-State Circuits 44(5), 1415–1424 (2009)

    Article  Google Scholar 

  59. Seeger, K.: Semiconductor Physics: An Introduction, 9th edn. Springer, Berlin (2004)

    Google Scholar 

  60. Shih, W.K., Rios, R., Packan, P., Mistry, K., Abbott, T.: A general partition scheme for gate leakage current suitable for MOSFET compact models. In: IEDM Tech. Dig., pp. 293–296 (2001)

    Google Scholar 

  61. Sze, S.M., Ng, K.K.: Physics of Semiconductor Devices, 3rd edn. Wiley, New York (2006)

    Book  Google Scholar 

  62. Taur, Y., Ning, T.: Fundamentals of Modern VLSI Devices. Cambridge University Press, Cambridge (1998)

    Google Scholar 

  63. Taylor, G.W.: The effects of two-dimensional charge sharing on the above-threshold characteristics of short-channel IGFETS. Solid-State Electron. 22(8), 701–717 (1979)

    Article  Google Scholar 

  64. Tsividis, Y.: Operation and Modeling of the MOS Transistor, 2nd edn. McGraw-Hill, New York (1999)

    Google Scholar 

  65. Tsu, R., Esaki, L.: Tunneling in a finite superlattice. Appl. Phys. Lett. 22, 562–564 (1973)

    Article  Google Scholar 

  66. van der Ziel, A., Chenette, E.R.: Noise in solid state devices. IEEE Trans. Electron Devices 46, 313 (1978)

    Google Scholar 

  67. van Langevelde, R.: A compact MOSFET model for distortion analysis in analog circuit design. Ph.D. thesis (1998)

    Google Scholar 

  68. van Langevelde, R., Gildenblat, G.: PSP: An Advanced Surface-Potential-Based MOSFET Model. Springer, Dordrecht (2006), Chap. 2, pp. 22–69

    Google Scholar 

  69. van Langevelde, R., Klaassen, F.M.: Accurate drain conductance modeling for distortion analysis in MOSFETs. In: IEDM Tech. Dig., pp. 313–316 (1997)

    Google Scholar 

  70. van Langevelde, R., Klaassen, F.M.: An explicit surface-potential-based MOSFET model for circuit simulation. Solid-State Electron. 44, 409–418 (2000)

    Article  Google Scholar 

  71. van Langevelde, R., Paasschens, J.C.J., Scholten, A.J., Havens, R.J., Tiemeijer, L.F., Klaassen, D.B.M.: New compact model for induced gate current noise. In: IEDM Tech. Dig., pp. 867–870 (2003)

    Google Scholar 

  72. van Langevelde, R., Scholten, A.J., Duffy, R., Cubaynes, F.N., Knitel, M.J., Klaassen, D.B.M.: Gate current modeling: ∆l extraction and impact on RF performance. In: IEDM Tech. Dig., pp. 289–292 (2001)

    Google Scholar 

  73. van Langevelde, R., Scholten, A.J., Havens, R.J., Tiemeijer, L.F., Klaassen, D.B.M.: Advanced compact MOS modelling. In: Proc. Eur. Solid-State Device Res. Conf., pp. 81–88 (2001)

    Google Scholar 

  74. van Langevelde, R., Scholten, A.J., Klaassen, D.B.M.: Physical background of MOS Model 11. Nat. Lab. Unclassified Report, NL-TN 2003/00239 (2003). http://www.nxp.com/models/mos_models/model11/.

  75. van Langevelde, R., Scholten, A.J., Klaassen, D.B.M.: Recent enhancements of MOS model 11. In: Tech. Proc. Nanotechnol. Conf., pp. 60–65 (2004)

    Google Scholar 

  76. Victory, J., Yan, Z., Gildenblat, G., McAndrew, C.C., Zheng, J.: A physically based, scalable MOS varactor model and extraction methodology for RF applications. IEEE Trans. Electron Devices 52(7), 1343–1353 (2005)

    Article  Google Scholar 

  77. Wang, H., Chen, T.L., Gildenblat, G.: Quasi-static and non-quasi-static compact MOSFET models based on symmetrically linearization of the bulk and inversion charges. IEEE Trans. Electron Devices 50(11), 2262–2272 (2003)

    Article  Google Scholar 

  78. Wang, H., Gildenblat, G.: Scattering matrix based compact MOSFET model. In: IEDM Tech. Dig., pp. 125–128 (2002)

    Google Scholar 

  79. Wang, H., Li, X., Wu, W., Gildenblat, G., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: A unified non-quasi-static MOSFET model for large-signal and small-signal simulations. IEEE Trans. Electron Devices 53(9), 2035–2043 (2006)

    Article  Google Scholar 

  80. Ward, D.E., Dutton, R.W.: A charge-oriented model for MOS transistor capacitances. IEEE J. Solid-State Circuits 13, 703–708 (1978)

    Article  Google Scholar 

  81. Watts, J., McAndrew, C.C., Enz, C., Galup-Montoro, C., Gildenblat, G., Hu, C., van Langevelde, R., Miura-Mattausch, M., Rios, R., Sah, C.T.: Advanced compact models for MOSFETs. In: Tech. Proc. Workshop on Compact Modeling, pp. 3–12 (2005)

    Google Scholar 

  82. Wright, P.J., Saraswat, K.C.: Thickness limitations of SiO2 gate dielectrics for MOS ULSI. IEEE Trans. Electron Devices 37, 1990 (1884–1892)

    Google Scholar 

  83. Wu, W., Chen, T.L., Gildenblat, G., McAndrew, C.C.: Physics-based mathematical conditioning of the MOSFET surface potential equation. IEEE Trans. Electron Devices 51(7), 1196–1199 (2004)

    Article  Google Scholar 

  84. Wu, W., Li, X., Wang, H., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C.: SP-SOI: A third generation surface potential based compact SOI MOSFET model. In: Proc. IEEE Custom Integr. Circuits Conf., pp. 819–822 (2005)

    Google Scholar 

  85. Wu, W., Li, X., Gildenblat, G., Workman, G., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M., Watts, J.: PSP-SOI: A surface potential based compact model of partially depleted SOI MOSFETs (invited). In: Proc. IEEE Custom Integr. Circuits Conf., pp. 41–48 (2007)

    Google Scholar 

  86. Wu, W., Li, X., Gildenblat, G., Workman, G.O., Veeraraghavan, S., McAndrew, C.C., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: A compact model for valence-band electron tunneling current in partially depleted SOI MOSFETs. IEEE Trans. Electron Devices 54(2), 316–322 (2007)

    Article  Google Scholar 

Download references

Acknowledgments

This work is supported in part by the Semiconductor Research Corporation and by the Compact Model Council (CMC). The detailed evaluation by the CMC members of several versions of the PSP model is deeply appreciated. The authors are much indebted to Dr. C.C. McAndrew for the numerous discussions of the material presented in this chapter. We are grateful to Dr. J. Watts for the test data shown in Fig. 1.14 and to G. Dessai for reading the manuscript and numerous useful comments.

Author information

Authors and Affiliations

  1. Ira A. Fulton School of Engineering, Department of Electrical Engineering, Arizona State University, Tempe, AZ, 85287, USA

    Gennady Gildenblat, Weimin Wu & Xin Li

  2. Philips Research Europe, 5656 AE, Eindhoven, The Netherlands

    Ronald van Langevelde

  3. NXP-TSMC Research Center, 5656 AE, Eindhoven, The Netherlands

    Andries J. Scholten, Geert D. J. Smit & Dirk B. M. Klaassen

Authors
  1. Gennady Gildenblat
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Weimin Wu
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Xin Li
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Ronald van Langevelde
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Andries J. Scholten
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Geert D. J. Smit
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Dirk B. M. Klaassen
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Gennady Gildenblat .

Editor information

Editors and Affiliations

  1. , Sch Elect Comptr & Energy Engr, Arizona State University, University Drive and Mill Avenue, Tempe, 85287-9309, Arizona, USA

    Gennady Gildenblat

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer Science+Business Media B.V.

About this chapter

Cite this chapter

Gildenblat, G. et al. (2010). Surface-Potential-Based Compact Model of Bulk MOSFET. In: Gildenblat, G. (eds) Compact Modeling. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-8614-3_1

Download citation

  • DOI: https://doi.org/10.1007/978-90-481-8614-3_1

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-8613-6

  • Online ISBN: 978-90-481-8614-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation