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Wide Dynamic Range Mobile TV Front-End Architecture

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Nanometer CMOS RFICs for Mobile TV Applications

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

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Abstract

This chapter presents a design example of a 65 nm CMOS chip that integrates the wide dynamic range DVB-H front-end architecture described in the previous chapter with an RF power level indicator circuit. The front-end consists of the wideband noise-cancelling LNA presented in Chapter 3 and the RF passive attenuator presented in Chapter 4. A power level indicator circuit will provide an automatic gain control function to the mobile TV front-end architecture. The chapter concludes by presenting some experimental results for this test chip.

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Notes

  1. 1.

    The window between the upper threshold and the lower threshold should be larger than the gain step.

Reference

  1. J.M. Stevenson, P. Hisayasu, A. Deiss, B. Abesingha, K. Beumer, J. Esquivel, A multi-standard analog and digital TV tuner for cable and terrestrial applications, in IEEE International Solid-State Circuits Conference, San Francisco, February 2007, pp. 210–211

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Correspondence to Ahmed A. Youssef .

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© 2010 Springer Science+Business Media B.V.

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Youssef, A.A., Haslett, J. (2010). Wide Dynamic Range Mobile TV Front-End Architecture. In: Nanometer CMOS RFICs for Mobile TV Applications. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-8604-4_5

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  • DOI: https://doi.org/10.1007/978-90-481-8604-4_5

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  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-8603-7

  • Online ISBN: 978-90-481-8604-4

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