Abstract
Evaluating circuit and system performance using carbon nanotube transistors (CNFET) is important to predict the prospect of this technology. For this purpose, this chapter presents a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. The simple quasi-analytical model is seen to be effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. An estimation of the parasitic fringe capacitance in state-of-the-art CNFET geometries is also provided which impacts the overall performance of CNFET circuits. It is observed that the device width should be significantly reduced in order to achieve the superior performance of intrinsic CNFET over silicon MOSFET in circuits and systems. However, unlike conventional MOSFET, nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and cylindrical gate geometry. This unique advantage can be effectively utilized in VLSI design to achieve better system performance under variations.
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Paul, B.C., Fujita, S., Okajima, M., Lee, T. (2010). The Prospect and Challenges of CNFET Based Circuits: A Physical Insight. In: Huang, C. (eds) Robust Computing with Nano-scale Devices. Lecture Notes in Electrical Engineering, vol 58. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-8540-5_6
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DOI: https://doi.org/10.1007/978-90-481-8540-5_6
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