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Design Methods and Tools for Improved Partial Dynamic Reconfiguration

  • Markus Rullmann
  • Renate Merker
Chapter

Abstract

In current FPGAs the overhead associated with partial dynamic reconfiguration limits the application of this method in system design. We review the origins of this overhead and present a novel approach to solve this problem. We introduce the reconfiguration state graph which is used to describe dynamic reconfiguration for individual resources and to assess reconfiguration cost. We present new method to map reconfigurable modules to resources such that the reconfiguration cost are small. The method can be applied to both digital circuits and dataflow graphs. We demonstrate that we can exploit the trade-off between resource requirements and reconfiguration cost by a unique high-level synthesis tool. We further discuss how our methodology can be integrated into a design flow for efficient runtime reconfigurable systems.

Keywords

Simulated Annealing Algorithm Input Graph Resource Type Partial Dynamic Register Transfer Level 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.Technische Universität DresdenDresdenGermany

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