Evaluation and Design Methods for Processor-Like Reconfigurable Architectures

  • Sven EisenhardtEmail author
  • Thomas Schweizer
  • Julio Oliveira Filho
  • Tommy Kuhn
  • Wolfgang Rosenstiel


This chapter focuses on the utilization of fast reconfiguration to optimize area, performance, and power. The results are quantified by a synthesizable architecture model. In order to assure good applicability of the research, a C-compiler is co-developed with the architecture. This chapter provides an overview of the optimization techniques and a summary of current evaluation results.


Fast Fourier Transform Clock Cycle Design Space Exploration Context Memory Trilinear Interpolation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  • Sven Eisenhardt
    • 1
    Email author
  • Thomas Schweizer
    • 1
  • Julio Oliveira Filho
    • 1
  • Tommy Kuhn
    • 1
  • Wolfgang Rosenstiel
    • 1
  1. 1.Department of Computer Engineering, Wilhelm-Schickard-Institute for Computer ScienceUniversity of TübingenTübingenGermany

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