Abstract
This chapter focuses on the utilization of fast reconfiguration to optimize area, performance, and power. The results are quantified by a synthesizable architecture model. In order to assure good applicability of the research, a C-compiler is co-developed with the architecture. This chapter provides an overview of the optimization techniques and a summary of current evaluation results.
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Eisenhardt, S., Schweizer, T., Oliveira Filho, J., Kuhn, T., Rosenstiel, W. (2010). Evaluation and Design Methods for Processor-Like Reconfigurable Architectures. In: Platzner, M., Teich, J., Wehn, N. (eds) Dynamically Reconfigurable Systems. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3485-4_5
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DOI: https://doi.org/10.1007/978-90-481-3485-4_5
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