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BER Estimation for Non-linear Clock and Data Recovery Circuit

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Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 51)

Abstract

In order to expedite the BER testing procedure, in Chapter 3, we developed a BER estimation technique for high-speed serial interfaces that incorporate a linear CDR circuit. However, this technique is not applicable to bang–bang (BB) CDR circuits, which have gained popularity due to their amenities to high-speed serial link applications. Because the BB phase detector in a CDR circuit behaves non-linearly with respect to the input jitter, its jitter transfer function varies significantly with respect to the jitter magnitude [44–46]. Such variations do not exist for a linear CDR circuit. Thus, the jitter transfer dependency on the jitter magnitude has to be considered to accurately estimate the BER for a BB CDR circuit.

Several recent papers studied the characteristics of BB CDR circuits [44–46]. In [44], the jitter transfer’s dependency on the input jitter magnitude is first analyzed. Then, the jitter tolerance is examined and the maximum input jitter at a given frequency that a CDR loop can tolerate is predicted. This analysis is only applicable to PJ. Because RJ and DDJ are also present in practice, most standards require all these jitter components to be considered for jitter tolerance testing [4, 15]. Thus, jitter analysis considering only PJ would not be sufficient.

In this chapter, we propose a method for estimating the BER of a BB CDR circuit. We first extend the jitter transfer and tolerance analysis proposed in [44] for the case when the data consist of both PJ and RJ. Then, we derive the BER estimation equation based on this analysis. The equation also uses the jitter spectral information as input, which includes the rms value of the RJ and frequencies and amplitudes of the PJ components.

Keywords

Phase Error Charge Pump Loop Filter Jitter Frequency Jitter Tolerance 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

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    National Committee for Information Technology Standardization (NCITS) (2003) T11.2/ Project 1316-DT/ Rev 10.0, Fibre Channel-Methodologies for Jitter and Signal Quality Specification-MJSQ, 10 March 2003Google Scholar
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    Lee J et al. (Sept 2004) Analysis and modeling of bang–bang clock and data recovery circuits. IEEE J Solid State Circuit 39(9):1571–1580CrossRefGoogle Scholar
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    Walker RC (2003) Designing bang–bang plls for clock and data recovery in serial data transmission systems. In: Razavi B (ed) Phase-locking in high-performance systems, IEEE Press, New York, pp 34–45Google Scholar
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    Choi Y et al. (Nov 2003) Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery. IEEE Trans Circuit Syst II 50(11):775–783CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media B.V. 2010

Authors and Affiliations

  1. 1.Broadcom CorporationIrvineUSA
  2. 2.Santa Barbara College of Engineering Dept. Electrical & Computer EngineeringUniversity of CaliforniaSanta BarbaraUSA

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