BER Estimation for Non-linear Clock and Data Recovery Circuit
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In order to expedite the BER testing procedure, in Chapter 3, we developed a BER estimation technique for high-speed serial interfaces that incorporate a linear CDR circuit. However, this technique is not applicable to bang–bang (BB) CDR circuits, which have gained popularity due to their amenities to high-speed serial link applications. Because the BB phase detector in a CDR circuit behaves non-linearly with respect to the input jitter, its jitter transfer function varies significantly with respect to the jitter magnitude [44–46]. Such variations do not exist for a linear CDR circuit. Thus, the jitter transfer dependency on the jitter magnitude has to be considered to accurately estimate the BER for a BB CDR circuit.
Several recent papers studied the characteristics of BB CDR circuits [44–46]. In , the jitter transfer’s dependency on the input jitter magnitude is first analyzed. Then, the jitter tolerance is examined and the maximum input jitter at a given frequency that a CDR loop can tolerate is predicted. This analysis is only applicable to PJ. Because RJ and DDJ are also present in practice, most standards require all these jitter components to be considered for jitter tolerance testing [4, 15]. Thus, jitter analysis considering only PJ would not be sufficient.
In this chapter, we propose a method for estimating the BER of a BB CDR circuit. We first extend the jitter transfer and tolerance analysis proposed in  for the case when the data consist of both PJ and RJ. Then, we derive the BER estimation equation based on this analysis. The equation also uses the jitter spectral information as input, which includes the rms value of the RJ and frequencies and amplitudes of the PJ components.
KeywordsPhase Error Charge Pump Loop Filter Jitter Frequency Jitter Tolerance
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