Abstract
Dependable systems are obtained by means of extensive testing procedures and the incorporation of fault tolerance mechanisms encompassing error detection (on-line testing) and system recovery. In that context, the characterization of fault models that are both tractable and representative of actual faults constitute an essential basis upon which one can efficiently verify, design or assess dependable systems. On one hand, models should refer to erroneous behaviors that are as abstract and as broad as possible to allow for the definition and development of both generic fault tolerance mechanisms and cost-effective injection techniques. On the other hand, the models should definitely aim at matching the erroneous behaviors induced by real faults.
In this chapter, we focus on the representativeness of fault models with respect to physical faults for deriving relevant testing procedures as well as detection mechanisms and experimental assessment techniques. We first discuss the accuracy of logic fault models with respect to physical defects in the implementation of off-line/on-line testing mechanisms. Then, we show how the fault models are linked to the identification and implementation of relevant fault injection-based dependability assessment techniques.
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- 1.
EFCIS: Société pour l’Etude et la Fabrication de Circuits Intégrés Spéciaux, that has evolved to form ST Microelectronics, in the late 1990s.
- 2.
Recent work oriented towards the development of (fault injection-based) dependability benchmarks (e.g., see Kanoun and Spainhower 2008) has adapted the notions attached to the A and F domains to the ones of Workload and Faultload, respectively.
- 3.
These efforts include also the IFIP WG 10.4 SIG on Dependability Benchmarking (http://www.dependability.org/wg10.4/SIGDeB) and the European Project on Dependability Benchmarking – DBench - Project IST 2000–25425 (http://www.laas.fr/dbench).
- 4.
MARS (MAintainable Real-time System) is the distributed system developed at Vienna Univ. of Technology, that has evolved to the TTA and TTP concepts (Kopetz and Bauer 2003).
- 5.
Fail silence is intended to describe the behavior of a computer that fails “cleanly” by just stopping to send messages in case a failure occurs (Powell, 1994).
- 6.
Such a direct control on the injected fault is not possible in the case of the software-implemented fault injection technique used (see Section 8.3.2.4).
- 7.
If the error was not detected by the NUT itself, then the node has no error information available and sends only a status message.
- 8.
Due to the small number of NMIs observed, such an analysis was not carried out for SWIFI.
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Acknowledgements
The pioneering research reported in Section 8.2 was led by Christian Landrault at LAAS-CNRS. Incidentally, it constitutes his first work on hardware testing, topic on which he has eagerly contributed since then at LIRMM. We are really pleased that we have been given the opportunity to participate in this way to this special book! The authors would like to thank several colleagues and friends from EFCIS (now ST Microelectronics), ESPRIT project PDCS, IST project DBench and from IFIP WG 10.4 on Dependable Computing and Fault Tolerance, for the fruitful exchanges along the years on the various topics addressed in the Chapter. In particular, we are grateful to Alain Costes and Michel Diaz (LAAS-CNRS), and also X. Messonnier, P. Rousseau, and Michel Vergniault (EFCIS) for their helpful comments, suggestions, and assistance for the study reported in Section 8.2. For what concerns Section 8.3, thanks go to Jean-Claude Laprie and Karama Kanoun (LAAS-CNRS), Johan Kalrsson and Peter Folkesson (Chalmers U.), Hermann Kopetz, Günther Leber and Emmerich Fuchs (Vienna UT), for their contributions to the reflections carried out and to the comprehensive comparative study reported. This work was supported in part by DRET, EFCIS, ESPRIT project PDCS, IST project DBench, and IST network of excellence ReSIST. Jacques Galiay, whose contribution to the work on offline testing was essential, sadly deceased in the early 1980s, during a hike in the Alps mountains.
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Arlat, J., Crouzet, Y. (2010). Physical Fault Models and Fault Tolerance. In: Wunderlich, HJ. (eds) Models in Hardware Testing. Frontiers in Electronic Testing, vol 43. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3282-9_8
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