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Models for Power-Aware Testing

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Book cover Models in Hardware Testing

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 43))

Abstract

Power consumption of circuits and systems receives more and more attention. In test mode, power consumption is even more critical than in system model and has severe impact on reliability, yield and test costs. This chapter describes the different types and sources of test power. Power-aware techniques for test pattern generation, design for test and test data compression are presented which allow efficient power constrained testing with minimized hardware cost and test application time.

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Authors and Affiliations

  1. LIRMM/CNRS, 161rue Ada, 34392, Montpellier, France

    Patrick Girard

  2. Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, D-70569, Stuttgart, Germany

    Hans-Joachim Wunderlich

Authors
  1. Patrick Girard
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  2. Hans-Joachim Wunderlich
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Correspondence to Patrick Girard .

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Editors and Affiliations

  1. Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, Stuttgart, 70569, Germany

    Hans-Joachim Wunderlich

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Girard, P., Wunderlich, HJ. (2010). Models for Power-Aware Testing. In: Wunderlich, HJ. (eds) Models in Hardware Testing. Frontiers in Electronic Testing, vol 43. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3282-9_7

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  • DOI: https://doi.org/10.1007/978-90-481-3282-9_7

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  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-3281-2

  • Online ISBN: 978-90-481-3282-9

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