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Generalized Fault Modeling for Logic Diagnosis

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Models in Hardware Testing

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 43))

Abstract

To cope with the numerous defect mechanisms in nanoelectronic technology, more and more complex fault models have been introduced. Each model comes with its own properties and algorithms for test generation and logic diagnosis. In diagnosis, however, the defect mechanisms of a failing device are not known in advance, and algorithms that assume a specific fault model may fail. Therefore, diagnosis techniques have been proposed that relax fault assumptions or even work without any fault model. In this chapter, we establish a generalized fault modeling technique and notation. Based on this notation, we describe and classify existing models and investigate the properties of a fault model independent diagnosis technique.

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Authors and Affiliations

  1. Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, D-70569, Stuttgart, Germany

    Hans-Joachim Wunderlich & Stefan Holst

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  1. Hans-Joachim Wunderlich
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  2. Stefan Holst
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Correspondence to Hans-Joachim Wunderlich .

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  1. Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, Stuttgart, 70569, Germany

    Hans-Joachim Wunderlich

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Wunderlich, HJ., Holst, S. (2010). Generalized Fault Modeling for Logic Diagnosis. In: Wunderlich, HJ. (eds) Models in Hardware Testing. Frontiers in Electronic Testing, vol 43. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3282-9_5

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  • DOI: https://doi.org/10.1007/978-90-481-3282-9_5

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