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Models in Hardware Testing pp 71–103Cite as

Models for Delay Faults

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Part of the book series: Frontiers in Electronic Testing ((FRET,volume 43))

Abstract

In this chapter fault models used to model the effects of defects causing excessive circuit delays are discussed. Methods to generate tests to detect modeled faults and design for test methods to improve fault coverage are reviewed. Current work in detecting what are called small delay defects is discussed.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa, USA

    Sudhakar M. Reddy

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  1. Sudhakar M. Reddy
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Correspondence to Sudhakar M. Reddy .

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  1. Institut für Technische Informatik, Universität Stuttgart, Pfaffenwaldring 47, Stuttgart, 70569, Germany

    Hans-Joachim Wunderlich

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Reddy, S.M. (2010). Models for Delay Faults. In: Wunderlich, HJ. (eds) Models in Hardware Testing. Frontiers in Electronic Testing, vol 43. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3282-9_3

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  • DOI: https://doi.org/10.1007/978-90-481-3282-9_3

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