Skip to main content
SpringerLink
Log in
Book cover

Analog Circuit Design pp 43–59Cite as

High-Resolution and Wide-Bandwidth CMOS Pipeline AD Converters

  • Chapter
  • First Online:

  • 2203 Accesses

Abstract

High-resolution wide-bandwidth ADCs in nm-CMOS are key enablers in increasing the level of digitization and integration in cellular base station receivers. This paper discusses smart techniques to overcome the limitations of low supply voltage and low intrinsic device gain. A 14 b 100 MS/s ADC in 90 nm CMOS is described demonstrating that good power efficiency can be achieved in nm-CMOS with a low supply voltage.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. B.-G. Lee et al., “A 14 b 100 MS/s Pipelined ADC with a Merged Active S/H and First MDAC”, ISSCC Dig. Tech. Papers, pp. 248–249, Feb. 2008.

    Google Scholar 

  2. A. van Roermund et al., “Smart AD and DA Converters”, Proc. ISCAS, pp. 4062–4065, May 2005.

    Google Scholar 

  3. H. Van de Vel, B. Buter, H. van der Ploeg, M. Vertregt, G. Geelen and E. Paulus, “A 1.2 V 250 mW 14b 100MS/s Digitally Calibrated Pipeline ADC in 90 nm CMOS”, VLSI Circuits Symp. Dig., pp. 74–75, Jun. 2008.

    Google Scholar 

  4. H. Van de Vel, B.A.J. Buter, H. van der Ploeg, M. Vertregt, G.J.G.M. Geelen and E.J.F. Paulus, “A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS”, IEEE J. Solid-State Circuits, vol. 44, pp. 1047–1056, Apr. 2009.

    Article  Google Scholar 

  5. S.H. Lewis and P.R. Gray, “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter”, IEEE J. Solid-State Circuits, vol. SC-22, pp. 954–961, Dec. 1987.

    Article  Google Scholar 

  6. W. Yang et al., “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input”, IEEE J. Solid-State Circuits, vol. 36, pp. 1931–1936, Dec. 2001.

    Article  Google Scholar 

  7. P. Bogner et al., “A 14 b 100 MS/s Digitally Self-Calibrated Pipelined ADC in 0. 13 μm CMOS”, ISSCC Dig. Tech. Papers, pp. 832–833, Feb. 2006.

    Google Scholar 

  8. B. Murmann and B.E. Boser, “A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”, IEEE J. Solid-State Circuits, vol. 38, pp. 2040–2050, Dec. 2003.

    Article  Google Scholar 

  9. J.K. Fiorenza et al., “Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies”, IEEE J. Solid-State Circuits, vol. 41, pp. 2658–2668, Dec. 2006.

    Article  Google Scholar 

  10. M. Anthony, E. Kohler, J. Kurtze, L. Kushner and G. Sollner, “A Process-Scalable Low-Power Charge-Domain 13-bit Pipeline ADC”, VLSI Circuits Symp. Dig., pp. 222–223, Jun. 2008.

    Google Scholar 

  11. B. Murmann, “A/D Converter Trends: Power Dissipation, Scaling and Digitally Assisted Architectures”, Proc. CICC, pp. 105–112, Sep. 2008.

    Google Scholar 

  12. B.-S. Song, S.-H. Lee and M.F. Tompsett, “A 10-b 15-MHz CMOS Recycling Two-Step A/D Converter”, IEEE J. Solid-State Circuits, vol. 25, pp. 1328–1338, Dec. 1990.

    Article  Google Scholar 

  13. A.N. Karanicolas et al., “A 15-b 1-Msample/s Digitally Self-Calibrated Pipeline ADC”, IEEE J. Solid-State Circuits, vol. 28, pp. 1207–1215, Dec. 1993.

    Article  Google Scholar 

  14. I. Galton, “Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters”, IEEE Trans. Circuits and Systems II, pp. 185–196, Mar. 2000.

    Google Scholar 

  15. P. Wambacq and W. Sansen, “Distortion Analysis of Analog Integrated Circuits”, Kluwer, 1998.

    Google Scholar 

  16. K. Bult, “Analog Design in Deep Sub-Micron CMOS”, Proc. ESSCIRC, pp. 126–132, Sep. 2000.

    Google Scholar 

  17. A.-J. Annema, B. Nauta, R. van Langevelde and H. Tuinhout, “Analog Circuits in Ultra-Deep-Submicron CMOS”, IEEE J. Solid-State Circuits, vol. 40, pp. 132–143, Jan. 2005.

    Article  Google Scholar 

  18. S. Limotyrakis, S.D. Kulchycki, D.K. Su and B.A. Wooley, “A 150-MS/s 8-b 71-mW CMOS Time-Interleaved ADC”, IEEE J. Solid-State Circuits, vol. 40, pp. 1057–1067, May 2005.

    Article  Google Scholar 

  19. Y. Chiu, P.R. Gray and B. Nikolic, “A 14-b 12-MS/s CMOS Pipeline ADC With Over 100-dB SFDR”, IEEE J. Solid-State Circuits, vol. 39, pp. 2139–2151, Dec. 2004.

    Article  Google Scholar 

Download references

Acknowledgements

The author would like to thank Berry Buter, Maarten Vertregt, Gerard van der Weide, Govert Geelen, Edward Paulus and Hendrik van der Ploeg for contributions to this work, and Joost Briaire, Kostas Doris, Pieter van Beek, Marcel Pelgrom and other members of the High-Speed Data Converter cluster for many fruitful discussions.

Author information

Authors and Affiliations

  1. NXP Semiconductors, Eindhoven, The Netherlands

    Hans Van de Vel

Authors
  1. Hans Van de Vel
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Hans Van de Vel .

Editor information

Editors and Affiliations

  1. Dept. Electrical Engineering, Eindhoven University of Technology, Eindhoven, 5600 MB, Netherlands

    Arthur H. M. Roermund

  2. Avondster 6, Kuurne, 8520, Belgium

    Herman Casier

  3. Dept. Electrical Engineering (ESAT), Katholieke Universiteit Leuven, Kasteelpark Arenberg 10, Leuven, 3001, Belgium

    Michiel Steyaert

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer Science+Business Media B.V.

About this chapter

Cite this chapter

Van de Vel, H. (2010). High-Resolution and Wide-Bandwidth CMOS Pipeline AD Converters. In: Roermund, A., Casier, H., Steyaert, M. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3083-2_3

Download citation

  • DOI: https://doi.org/10.1007/978-90-481-3083-2_3

  • Published:

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-3082-5

  • Online ISBN: 978-90-481-3083-2

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation