Abstract
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities and burgeoning die sizes in multi-core architectures. As already seen in the previous chapter, partitioning a larger die into smaller segments and then stacking them in a 3D fashion can significantly reduce latency and energy consumption. Such benefits emanate from the notion that inter-wafer distances are negligible compared to intra-wafer distances. This attribute substantially reduces global wiring length in 3D chips.
The work in this chapter expands on the previous chapter by further integrating the increasingly popular idea of packet-based Networks-on-Chip into a 3D setting. While NoCs have been studied extensively in the 2D realm, the microarchitectural ramifications of moving into the third dimension have yet to be fully explored. This chapter presents a detailed exploration of inter-strata communication architectures in 3D NoCs.
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Nicopoulos, C., Narayanan, V., Das, C.R. (2009). A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]. In: Network-on-Chip Architectures. Lecture Notes in Electrical Engineering, vol 45. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3031-3_9
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DOI: https://doi.org/10.1007/978-90-481-3031-3_9
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