Abstract
It has already been established that long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communication infrastructures and three-dimensional (3D) designs where multiple device layers are stacked together.
Considering the current trends towards increasing use of chip multiprocessing, it is timely to consider 3D chip multiprocessor design and memory networking issues, especially in the context of data management in large L2 caches. The overall goal of this chapter is to study the challenges for L2 design and management in 3D chip multiprocessors.
The work presented hereafter constitutes a natural continuation of the previous chapter, which hybridized two seemingly disparate interconnection architectures – namely a bus and an on-chip network – to extract combined overall benefits. While Chapter 7 explored this concept in the traditional, 2D context, Chapter 8 will extend the exploration to the third dimension.
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J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy, “Introduction to the Cell Multiprocessor,” IBM Journal of Research and Development, vol. 49, pp. 589-604, 2005.
P. Kongetira, K. Aingaran, and K. Olukotun, “Niagara: a 32-way multithreaded Sparc processor,” in IEEE Micro, vol. 25, pp. 21-29, 2005.
T. D. Richardson, C. Nicopoulos, D. Park, V. Narayanan, X. Yuan, C. Das, and V. Degalahal, “A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks,” in Proceedings of the International Conference on VLSI Design, pp. 657–664, 2006.
J. Kim, D. Park, C. Nicopoulos, N. Vijaykrishnan, and C. R. Das, “Design and analysis of an NoC architecture from performance, reliability and energy perspective,” in Proceedings of the Symposium on Architecture for Networking and Communications Systems (ANCS), pp. 173 - 182, 200
Kim Changkyu, Doug Burger, and S. W. Keckler, “An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches,” in Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2002.
S. Das, A. Fan, K.-N. Chen, C. S. Tan, N. Checka, and R. Reif, “Technology, performance, and computer-aided design of three-dimensional integrated circuits,” in Proceedings of the International Symposium on Physical Design, 2004.
P. Morrow, M. J. Kobrinsky, S. Ramanathan, C. M. Park, M. Harmes, V. Ramachandrarao, H. Park, G. Kloster, S. List, and S. Kim, “Wafer-Level 3D Interconnects Via Cu Bonding,” in Proceedings of the 21st Advanced Metallization Conference, 2004
P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, and G. Hallberg, “Simics: A full system simulation platform,” in IEEE Computer, vol. 35(2), pp. 50-58, 2002.
Standard Performance Evaluation Corporation, “SPEC OMP,” http://www.spec.org/hpg/omp2001/, December 2005.
Z. Chishti, M. D. Powell, and T. N. Vijaykumar, “Distance associativity for high-performance energy-efficient non-uniform cache architectures,” in Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 55-66, 2003.
Z. Chishti, M. D. Powell, and T. N. Vijaykumar, “Optimizing replication, communication, and capacity allocation in CMPs,” in Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), pp. 357-368, 2005.
A. Zhang and K. Asanovic, “Victim replication: Maximizing capacity while hiding wire delay in tiled chip multiprocessors,” in Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), 2005.
B. M. Beckmann and D. A. Wood, “Managing Wire Delay in Large Chip-Multiprocessor Caches,” in Proceedings of the 37th International Symposium on Microarchitecture (MICRO), pp. 319-330, 2004.
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, and S. W. Keckler, “A NUCA substrate for flexible CMP cache sharing,” in Proceedings of the 19th Annual International Conference on Supercomputing (ICS), 2005.
Y. Deng and W. Maly, “2.5D system integration: a design driven system implementation schema,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 450-455, 2004.
J. W. Joyner, P. Zarkesh-Ha, and J. D. Meindl, “A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC),” in Proceedings of the 14th Annual IEEE International ASIC/SOC Conference, pp. 147-151, 2001.
S.-M. Jung, J. Jang, W. Cho, J. Moon, K. Kwak, B. Choi, B. Hwang, H. Lim, J. Jeong, J. Kim, and K. Kim, “The revolutionary and truly 3-dimensional 25F/sup 2/ SRAM technology with the smallest S/sup 3/ ( stacked single-crystal Si) cell, 0.16um/sup 2/, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAM,” in Digest of Technical Papers of the Symposium on VLSI Technology, pp. 228-229, 2004.
Y. F. Tsai, Y. Xie, N. Vijaykrishnan, and M. J. Irwin, “Three-Dimensional Cache Design Exploration Using 3D Cacti,” in Proceedings of the International Conference on Computer Design (ICCD), 2005.
B. Black, D. W. Nelson, C. Webb, and N. Samra, “3D processing technology and its impact on iA32 microprocessors,” in Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 316-318, 2004.
M. Ieong, K. W. Guarini , V. Chan, K. Bernstein, R. Joshi , J. Kedzierski, and W. Haensch, “Three dimensional CMOS devices and integrated circuits,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 207-213, 2003.
W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon, “Demystifying 3D ICs: the pros and cons of going vertical,” in IEEE Design & Test of Computers, vol. 22, pp. 498-510, 2005.
A. Young, “Perspectives on 3D-IC Technology,” Presentation at the 2nd Annual Conference on 3D Architectures for Semiconductor Integration and Packaging, June 2005.
K. Puttaswamy and G. H. Loh, “Implementing Caches in a 3D Technology for High Performance Processors,” in Proceedings of the International Conference on Computer Design (ICCD), pp. 525-532, 2005.
J. Cong and Z. Yan, “Thermal via planning for 3-D ICs,” in Proceedings of the International Conference on Computer-Aided Design (ICCAD), pp. 745-752, 2005.
B. Goplen and S. Sapatnekar, “Efficient thermal placement of standard cells in 3D ICs using a force directed approach,” in Proceedings of the International Conference on Computer-Aided Design (ICCAD), pp. 86-89, 2003.
B. Dang, P. Joseph, M. Bakir, T. Spencer, P. Kohl, and J. Meindl, “Wafer-level microfluidic cooling interconnects for GSI,” in Proceedings of the International Interconnect Technology Conference, pp. 180-182, 2005.
W. L. Hung, G. M. Link, X. Yuan, N. Vijaykrishnan, and M. J. Irwin, “Interconnect and thermal-aware floorplanning for 3D microprocessors,” in Proceedings of the International Symposium on Quality Electronic Design (ISQED), pp. 98-104, 2006.
B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCaule, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, and C. Webb, “Die Stacking (3D) Microarchitecture,” in Proceedings of the International Symposium on Microarchitecture (MICRO), pp. 469-479, 2006.
J. Cong and Z. Yan, “Thermal-driven multilevel routing for 3D ICs,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), vol. 1, pp. 121-126 Vol. 1, 2005.
A. Zeng, J. Lu, K. Rose, and R. J. Gutmann, “First-Order Performance Prediction of Cache Memory with Wafer-Level 3D Integration,” in IEEE Design and Test of Computers, vol. 22(6), pp. 548-555, 2005.
C. C. Liu, I. Ganusov, M. Burtscher, and T. Sandip, “Bridging the processor-memory performance gap with 3D IC technology,” in IEEE Design & Test of Computers, vol. 22, pp. 556-564, 2005.
T. Kgil, S. D’Souza, A. Saidi, N. Binkert, R. Dreslinski, T. Mudge, S. Reinhardt, and K. Flautner, “PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor,” in Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2006.
S. Mysore, B. Agrawal, N. Srivastava, S. C. Lin, K. Banerjee, and T. Sherwood, “Introspective 3D chips,” in Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS),
G. M. Link and N. Vijaykrishnan, “Thermal trends in emerging technologies,” in Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED), pp. 8, 2006.
P. Shivakumar and N. P. Jouppi, “Cacti 3.0: An integrated cache timing, power and area model,” Technical Report, Compaq Computer Corporation, August 2001.
Sun Microsystems Inc, “Sun UltraSPARC T1 Overview,” http://www.sun.com/processors/ UltraSPARC-T1/, December 2005.
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Nicopoulos, C., Narayanan, V., Das, C.R. (2009). Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]. In: Network-on-Chip Architectures. Lecture Notes in Electrical Engineering, vol 45. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3031-3_8
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DOI: https://doi.org/10.1007/978-90-481-3031-3_8
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