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Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]

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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 45))

Abstract

It has already been established that long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communication infrastructures and three-dimensional (3D) designs where multiple device layers are stacked together.

Considering the current trends towards increasing use of chip multiprocessing, it is timely to consider 3D chip multiprocessor design and memory networking issues, especially in the context of data management in large L2 caches. The overall goal of this chapter is to study the challenges for L2 design and management in 3D chip multiprocessors.

The work presented hereafter constitutes a natural continuation of the previous chapter, which hybridized two seemingly disparate interconnection architectures – namely a bus and an on-chip network – to extract combined overall benefits. While Chapter 7 explored this concept in the traditional, 2D context, Chapter 8 will extend the exploration to the third dimension.

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Correspondence to Chrysostomos Nicopoulos .

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Nicopoulos, C., Narayanan, V., Das, C.R. (2009). Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]. In: Network-on-Chip Architectures. Lecture Notes in Electrical Engineering, vol 45. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3031-3_8

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  • DOI: https://doi.org/10.1007/978-90-481-3031-3_8

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