The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15]

Abstract

Systems-on-Chip (SoCs) have become the design methodology of choice for a multitude of applications, spawning a number of on-chip communication-related challenges. So far, the two dominant architectural choices for implementing efficient communication fabrics for SoCs have been transaction-based processor interconnect buses and packet-based Networks-on-Chip (NoC). Transaction-based buses have in-built design choices that constrain their application, making them unsuitable as efficient SoC interconnects. Networks-on-Chip, on the other hand, suffer from inconsistent latencies and deterioration of performance at high data injection rates due to their network pedigree.

In this chapter, we aim to address this disconnect between buses and NoCs in an attempt to develop a highly scalable and efficient interconnection framework that captures the intricacies of both heterogeneous Multi-Processor SoCs (MPSoC) and homogeneous Chip Multiprocessors (CMP). Before embarking on this quest, we first evaluate thoroughly existing interconnect types, including the newly-proposed Code-Division Multiple-Access (CDMA) interconnects. Building on this exploratory phase, a new transaction-less bus, the Dynamic Time-Division Multiple-Access (dTDMA) bus, is then developed and analyzed, and its performance quantified and compared to existing buses and NoCs. The dTDMA bus was specifically architected to overcome the weaknesses of transaction-based buses and be amenable to bandwidth-hungry SoC applications.