Abstract
Chapter 5 described how on-chip routers are increasingly susceptible to various hard and soft faults, which themselves are a natural consequence of diminutive feature sizes. In addition to these hindrances, the last couple of years have witnessed the emergence of yet another artifact of deep sub-micron technology, Process Variation (PV). PV is a consequence of manufacturing imperfections, which may lead to degraded performance and even erroneous behavior. In this chapter, the author presents the first comprehensive evaluation of NoC susceptibility to PV effects and proposes an array of architectural improvements in the form of a new router design – called SturdiSwitch – to increase resiliency to these effects. Through extensive re-engineering of critical components, SturdiSwitch provides increased immunity to PV while improving performance and increasing area and power efficiency.
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Nicopoulos, C., Narayanan, V., Das, C.R. (2009). On the Effects of Process Variation in Network-on-Chip Architectures [45]. In: Network-on-Chip Architectures. Lecture Notes in Electrical Engineering, vol 45. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3031-3_6
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DOI: https://doi.org/10.1007/978-90-481-3031-3_6
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