Abstract
Network-on-chip architectures are required to not only provide ultra-low latency, but also occupy a small footprint and consume as little energy as possible. Further, reliability is rapidly becoming a major challenge in deep sub-micron technologies due to the increased prominence of permanent faults resulting from accelerated aging effects and manufacturing/testing challenges.
Towards the goal of designing low-latency, energy-efficient and reliable on-chip communication networks, we propose a novel fine-grained modular router architecture. while Chapter 3 focused solely on the router buffers, this chapter will attempt to optimize several of the remaining core micro-architectural components. In particular, the proposed architecture employs decoupled parallel arbiters and uses smaller crossbars for row and column connections to reduce output port contention probabilities as compared to existing designs. Furthermore, the router employs a new switch allocation technique known as “Mirroring Effect” to reduce arbitration depth and increase concurrency. In addition, the modular design permits graceful degradation of the network in the event of permanent faults and also helps to reduce the dynamic power consumption. Our simulation results indicate that in an 8 × 8 mesh network, the proposed architecture reduces packet latency by 4–40% and power consumption by 6–20% as compared to two existing router architectures. Evaluation using a combined performance, energy and fault-tolerance metric indicates that the proposed architecture provides 35–50% overall improvement compared to the two earlier routers.
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
R. Kumar, V. Zyuban, and D. M. Tullsen, “Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling,” in Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), pp. 408–419, 2005.
W. Hangsheng, L. S. Peh, and S. Malik, “Power-driven design of router microarchitectures in on-chip networks,” in Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 105–116, 2003.
R. Marculescu, “Networks-on-chip: the quest for on-chip fault-tolerant communication,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 8-12, 2003.
R. Mullins, A. West, and S. Moore, “Low-latency virtual-channel routers for on-chip networks,” in Proceedings of the International Symposium on Computer Architecture (ISCA), pp. 188-197, 2004.
L. S. Peh and W. J. Dally, “A delay model and speculative architecture for pipelined routers,” in Proceedings of the 7th International Symposium on High-Performance Computer Architecture (HPCA), pp. 255-266, 2001.
W. Hangsheng, L. S. Peh, and S. Malik, “A technology-aware and energy-oriented topology exploration for on-chip networks,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 1238-1243 Vol. 2, 2005.
J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, and C. R. Das, “A low latency router supporting adaptivity for on-chip interconnects,” in Proceedings of the Design Automation Conference (DAC), pp. 559-564, 2005.
C. A. Moritz, Y. Donald, and A. Agarwal, “SimpleFit: a framework for analyzing design trade-offs in Raw architectures,” in IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 12, pp. 730-742, 2001.
L. Shang, L. S. Peh, A. Kumar, and N. K. Jha, “Thermal Modeling, Characterization and Management of On-Chip Networks,” in Proceedings of the International Symposium on Microarchitecture (MICRO), pp. 67-78, 2004.
P. Partha Pratim, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, “Performance evaluation and design trade-offs for network-on-chip interconnect architectures,” in IEEE Transactions on Computers, vol. 54, pp. 1025-1040, 2005.
A. Ivanov and G. De Micheli, “Guest Editors’ Introduction: The Network-on-Chip Paradigm in Practice and Research,” in IEEE Design & Test of Computers, vol. 22, pp. 399-403, 2005.
J. Kim, W. J. Dally, B. Towles, and A. K. Gupta, “Microarchitecture of a high radix router,” in Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), pp. 420-431, 2005.
S. Chalasani and R. V. Boppana, “Fault-tolerance with multimodule routers,” in Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), pp. 201-210, 1996.
P. May, S. Bunchua, and D. S. Wills, “HiPER: a compact narrow channel router with hop-by-hop error correction,” IEEE Transactions on Parallel and Distributed Systems, vol. 13, pp. 485-498, 2002.
Y. Choi and T. M. Pinkston, “Evaluation of crossbar architectures for deadlock recovery routers,” in Journal of Parallel and Distributed Computing, vol. 61, pp. 49 - 78, 2001.
W. J. Dally and B. Towles, Principles and practices of interconnection networks: Morgan Kaufmann, 2003.
J. Duato, S. Yalamanchili, and L. Ni, “Interconnection networks: An engineering Approach.,” Los Alamitos, Calif., IEEE Computer Society, 1997.
H. Jingcao and R. Marculescu, “Energy-aware mapping for tile-based NoC architectures under performance constraints,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 233-239, 2003.
P. Barford and M. Crovella, “Generating representative Web workloads for network and server performance evaluation,” in Proceedings of the ACM SIGMETRICS Joint International Conference on Measurement and Modeling of Computer Systems, 1998.
B. Caminero, F. J. Quiles, J. Duato, D. S. Love, and S. Yalamanchili, “Performance Evaluation of the Multimedia Router with MPEG-2 Video Traffic,” in Proceedings of the International Workshop on Communication, Architecture, and Applications for Network-Based Parallel Computing, pp. 62-76, 1999.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2009 Springer Science+Business Media B.V.
About this chapter
Cite this chapter
Nicopoulos, C., Narayanan, V., Das, C.R. (2009). RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40]. In: Network-on-Chip Architectures. Lecture Notes in Electrical Engineering, vol 45. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3031-3_4
Download citation
DOI: https://doi.org/10.1007/978-90-481-3031-3_4
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-90-481-3030-6
Online ISBN: 978-90-481-3031-3
eBook Packages: EngineeringEngineering (R0)