Abstract
A generic NoC implementation consists of a number of Processing Elements (PE) arranged in a mesh-like grid, as shown in Fig. 2.1. The PEs may be of the same type, e.g., CPU, or of different type, e.g., audio cores, video cores, wireless transceivers, memory banks, etc. Each PE is connected to a local router through a Network Interface Controller (NIC); each router is, in turn, connected to adjacent routers forming a packet-based on-chip network. The NIC module packetizes/de-packetizes the data into/from the underlying interconnection network. The PE together with its NIC form a network node. Nodes communicate with each other by injecting data packets into the network. The packets traverse the network toward their destination, based on various routing algorithms and control flow mechanisms.
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© 2009 Springer Science+Business Media B.V.
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Nicopoulos, C., Narayanan, V., Das, C.R. (2009). A Baseline NoC Architecture. In: Network-on-Chip Architectures. Lecture Notes in Electrical Engineering, vol 45. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3031-3_2
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DOI: https://doi.org/10.1007/978-90-481-3031-3_2
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