Abstract
The continuing technology scale reduction into the deep sub-micron era has magnified the delay mismatch between gates and global wires. Wiring will significantly affect design decisions in the forthcoming billion-transistor chips, whether these are complex heterogeneous SoCs, or Chip Multi-Processors. Networks-on-Chip have surfaced as a possible solution to escalating wiring delays in future multi-core chips.
The design of efficient on-chip networks is impeded by inherently conflicting requirements: the NoC is expected to provide ultra-low latencies, while occupying as little silicon real-estate, and consuming as little energy, as possible. These three design strands engage in an elaborate tug-of-war, requiring extensive exploration to reach a delicate balance between all three. This intricate interplay is compounded even further by reliability and variability artifacts, which are emerging ominously as technology feature sizes dwindle. Consequently, the author presented a holistic approach to designing NoCs. To fully capture the complexity underlying the interconnect architecture, the design process in this volume was guided by a quintet of fundamental design drivers: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. The overall design exploration was divided into two threads: (a) MICRO-Architectural Innovations within the major NoC components, and (b) MACRO-Architectural Solutions at the system level.
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© 2009 Springer Science+Business Media B.V.
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Nicopoulos, C., Narayanan, V., Das, C.R. (2009). Conclusions and Future Work. In: Network-on-Chip Architectures. Lecture Notes in Electrical Engineering, vol 45. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3031-3_11
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DOI: https://doi.org/10.1007/978-90-481-3031-3_11
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