Abstract
Since the beginning of the new millennium, the world of digital system design has witnessed an unprecedented phenomenon: a rapid and persistent reduction in feature sizes well into the nanoscale realm. Advancements in device technology and fabrication techniques have enabled designers to tread into previously unchartered territories; integration of billions of transistors on-die is now a reality. At such integration levels, it is imperative to employ parallelism to effectively utilize the transistors [1].
Keywords
- Application Specific Integrate Circuit
- Negative Bias Temperature Instability
- Central Processing Unit
- Router Architecture
- Random Dopant Fluctuation
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Nicopoulos, C., Narayanan, V., Das, C.R. (2009). Introduction. In: Network-on-Chip Architectures. Lecture Notes in Electrical Engineering, vol 45. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3031-3_1
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