Variation-Aware Sizing: Background

Abstract

Chapter 1 discussed how the progress of Moore’s Law leads to increased process variations, which leads to significantly reduced circuit yields [Itrs2007]. Yield optimization/design centering for the sizing task can play a useful role within a statistical design toolset, to speed a designer’s overall robust-design effort. Accordingly, there has been much research effort aimed at building analog circuit yield optimizers. This chapter examines the problem, and reviews past approaches.

This chapter is organized as follows. Section 2.1.2 gives the problem formulation, followed by industrial-level specifications in Sect. 2.1.3. Section 2.2 reviews past approaches, starting with a baseline direct Monte Carlo and proceeding through several more advanced algorithms. Section 2.3 concludes.

A small leak will sink a great ship.

– Benjamin Franklin