Algorithmic/Architectural Level Refinement

Previous chapter discussed an elaborate design space exploration at algorithmic/ architectural level. The outcome of this energy-oriented design space exploration was a very coarse receiver architecture, together with its fundamental operating principles. Figure 5.1 shows the architecture of the Quadrature Analog Correlating IR-UWB receiver, which was selected as the most energy optimal alternative.

Due to the preceding design space exploration, the design task at architectural level is reduced to an algorithmic/architectural refinement. Starting from the outcome of the DSE, the QAC receiver's architecture and its operating algorithms will be refined further. In the first step, the necessary algorithms for data detection, synchronization, acquisition, and ranging will be designed. Where possible, multiple alternatives will be proposed and the most energy optimal solution will be selected.