High Speed Filter with Automatic Tuning Circuit

The high speed filters are discussed in the chapter. One application of the high speed filter is in the storage devices, such as the hard disk system. The signal from an HDD system can corrupt by distortion, noise and interference. The inter-symbol interference (ISI) would corrupt the signal source, and it would be the dominant non-ideality in high density detecting. The read channel, which performs the partial response maximum likelihood (PRML) method to reduce ISI, places an important role in the HDD system. Figure 5.1 shows the architecture of hard disk front-end. The preamplifier reduces the noise from the magnetic media, and then the signal is fed to the variable gain amplifier (VGA). The filter performs simple signal equal ization. After simple equalization, an analog-to-digital converter (ADC) with 6-bit resolution is used. Finally, the digital signal processing (DSP) core performs com plete signal equalization. The DSP core also controls the gain and timing through the interface. The modern approach uses a fifth-order filter for magnitude equaliza tion, and other equalization is done in the digital processing. The fifth-order filter is composed by a one pole filter following the VGA and a fourth-order filter. The high speed fourth-order filter should have a linear phase. The details of a linear phase filter would be discussed in the next section. The other approach of high speed filter is the high speed wireless application, such as the ultra wideband (UWB) system.

The automatic tuning circuit, which compensates the effects caused by the corner variation in the fabrication process, is discussed in this chapter. Then, two imple mentations to the HDD and UWB system are introduced.