Motivation

Low-voltage VLSI circuits have received significant attention in recent years. The supply voltage has decreased following the advancement of process technology, and the operation frequency of CMOS can also go up higher than 100 GHz. The demands for nano-scale applications are mainly classified into technology-driven, design-driven, and market-driven. They are mainly to reduce the minimum feature size to scale down the chip area, to fabricate millions of transistors on a single chip to save cost, and to the increase market demands for communication electronic prod ucts. These demands seem to be independent of each other. However, the advances in VLSI technology, circuit design, and product market are actually interrelated.

In the past decade, CMOS technology has played a major role in the rapid ad vancement and the increased integration of VLSI systems. CMOS devices feature high input impedance, extremely low offset switches, high packing density, low switching power consumption, and thus can be easily scaled. The minimum feature size of a MOS transistor has been decreasing [1–3]. Current VLSI technology is scaled down to around 90 nm. Scaling down the transistor sizes can then integrate more circuit components in a single chip, so the circuit area and thus its cost will be reduced. Besides this economic consideration, smaller geometry usually lowers the parasitic capacitance, which leads to higher operating speed. When a MOS transis tor size is decreased, not only its channel length and width are reduced, but also the thickness of the gate oxide. As a MOS transistor has a thinner gate oxide, in order to prevent the transistor from breakdown due to higher electrical field across the gate oxide and to ensure its reliability, the supply voltage needs to be reduced [4–8]. Since the digital circuits are becoming more and more popular, the computer-aided design tools for digital circuits are getting matured, the digital circuits are certainly occupying most of the fabricated chip area, and the electrical characteristics of MOS transistors are getting optimized mainly for digital circuits. Switching to use nano-scale devices, digital circuits do not suffer the degradation of their performances too much.