This article introduces a template based technique in state encoding process to insert additional signals to STG with a small number. According to our method, complete state coding (CSC) property can be satisfied without using state graph tracing. Our method is useful for complicated asynchronous controllers, and also it can guarantee the other relevant properties, such as persistency and consistency. Our process begins with an encoding STG using Petri-net level in order to form a template STG. Then the projection to each non-input signals from an original STG is done. After that, we trace the projection to smaller state space. If the small state space shows conflicts, we have to insert balance signals from template STG. Unbalance signals are inserted after in case the state space still shows conflicts. Finally, we can get the STG with appropriate insertion points which is used to be projected for CSC support on each non-input signals. Asynchronous DMA controller is an example of our proposed method. The final part of this paper is concluded with a complexity comparison between our template based method with state based method and structural encoding method. It shows that the number of iterative signal removal according to our method is less than others.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
S.B. Park. Synthesis of Asynchronous VLSI circuit from Signal Transition Graph Specifications, Ph.D. thesis, Tokyo Institute of Technology, 1996.
J. Carmona, J. Cortadella. ILP models for the synthesis of asynchronous control circuits. In Proceedings of the International Conference Computer-Aided Design (ICCAD), pp. 818–825, November 2003.
J. Carmona and J. Cortadella. State encoding of large asynchronous controllers. In Proceedings of the ACM/IEEE Design Automation Conference, pp. 939–944, July 2006.
J. Carmona, J. Cortadella, and E. Pastor. A structural encoding technique for the synthesis of asynchronous circuits. In International Conference on Application of Concurrency to System Design, pp. 157–166, June 2001.
S. Sudeng and A. Thongtak FPGA Implementation of Quasi-Delay Insensitive Microprocessor. The World Congress on Engineering and Computer Science (WCECS2007), Clark Kerr Campus, University of California Berkeley, San Francisco, CA, USA on 24–26 October 2007.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 Springer Science+Business Media B.V
About this chapter
Cite this chapter
Sudeng, S., Thongtak, A. (2009). Template Based: A Novel STG Based Logic Synthesis for Asynchronous Control Circuits. In: Ao, SI., Gelman, L. (eds) Advances in Electrical Engineering and Computational Science. Lecture Notes in Electrical Engineering, vol 39. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-2311-7_6
Download citation
DOI: https://doi.org/10.1007/978-90-481-2311-7_6
Publisher Name: Springer, Dordrecht
Print ISBN: 978-90-481-2310-0
Online ISBN: 978-90-481-2311-7
eBook Packages: EngineeringEngineering (R0)