Novel Biomimetic Si Devices for Neuromorphic Computing Architecture

Part of the Cognitive Systems Monographs book series (COSMOS, volume 31)


Neuromorphic computing requires low-power devices and circuits in cross-point architecture. On-chip learning is a significant challenge that requires the implementation of learning rules like spike-timing-dependent plasticity (STDP)—a method that modifies synaptic strength depending upon the time correlation between the presynaptic and postsynaptic neuron spikes in a specific function. To implement this capability in phase-change memory (PCM) or resistance RAM (RRAM)-based cross-point arrays, two schemes have been proposed in the literature where the time correlations are captured by an address event representation scheme using an universal bus or superposition of long custom waveforms. In comparison, in biology, the pulses are sharp and the time correlation information is processed at the synapse by the natural dynamics of the synapse. These are attractive attributes for minimizing power and complexity/area. Another challenge is realizing an area- and power-efficient implementation of the electronic neuron. A leaky integrate-and-fire (LIF) neuron has been implemented using analog and digital circuits which are highly power and area inefficient. To improve area and power efficiency, we have recently proposed: (i) A Si diode-based synaptic device where the charge carrier internal dynamics is used to capture the time correlation based on sharp pulses (100\(\times \) sharper than custom waveforms to improve energy per spike) which can operate at 10\(^{3}\)–10\(^{6}\) times faster than biology (providing accelerated learning) and (ii) A compact Si neuronal device that has a 60\(\times \) area and 5\(\times \) power benefit compared to analog implementation of neurons. These are novel devices that are based on SiGe CMOS technology, and they are highly manufacturable. The synaptic devices are based on natural transients of the impact ionization-based n\(^{+}\) p n\(^{+}\) diode (I-NPN diode). STDP and Hebbian learning rules have been implemented. The neuron requires further modification of the I-NPN diode requiring a gating structure and some simple circuits. A leaky integrate-and-fire (LIF) neuron has also been demonstrated. Based on their device-level area and power efficiency, system-level power and area of neural networks will be highly enhanced.


Postsynaptic Neuron Subthreshold Slope Spike Neural Network TCAD Simulation Electron Barrier 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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© Springer (India) Pvt. Ltd. 2017

Authors and Affiliations

  1. 1.Department of Electrical EngineeringIIT BombayMumbaiIndia
  2. 2.Department of Electrical and Computer EngineeringNew Jersey Institute of TechnologyNewarkUSA

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